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formation and before placing orders for products or services
.
UG-IPQDRII-8.1
ii
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
Altera Corporation
Contents
Chapter 1. About This MegaCore Function
Release Information ...............................................................................................................................
Device Family Support .........................................................................................................................
Features ...................................................................................................................................................
General Description ...............................................................................................................................
OpenCore Plus Evaluation ..............................................................................................................
Performance and Resource Utilization ...............................................................................................
1–1
1–1
1–2
1–2
1–3
1–4
Chapter 2. Getting Started
Design Flow ............................................................................................................................................ 2–1
QDRII SRAM Controller Walkthrough .............................................................................................. 2–2
Create a New Quartus II Project .................................................................................................... 2–3
Launch IP Toolbench ....................................................................................................................... 2–4
Step 1: Parameterize ......................................................................................................................... 2–5
Step 2: Constraints ............................................................................................................................ 2–7
Step 3: Set Up Simulation ................................................................................................................ 2–7
Step 4: Generate ................................................................................................................................ 2–8
Simulate the Example Design ............................................................................................................ 2–11
Simulate with IP Functional Simulation Models ....................................................................... 2–11
Simulating With the ModelSim Simulator ................................................................................. 2–11
Simulating With Other Simulators .............................................................................................. 2–12
Simulating in Third-Party Simulation Tools Using NativeLink ............................................. 2–17
Edit the PLL .......................................................................................................................................... 2–18
Compile the Example Design ............................................................................................................ 2–19
Program a Device ................................................................................................................................ 2–21
Implement Your Design ..................................................................................................................... 2–21
Set Up Licensing .................................................................................................................................. 2–21
Chapter 3. Functional Description
Block Description ................................................................................................................................... 3–1
Control Logic .................................................................................................................................... 3–2
Resynchronization & Pipeline Logic ............................................................................................. 3–3
Datapath ............................................................................................................................................ 3–5
OpenCore Plus Time-Out Behavior .................................................................................................. 3–10
Interfaces & Signals ............................................................................................................................. 3–10
Interface Description ...................................................................................................................... 3–10
Signals .............................................................................................................................................. 3–22
Device-Level Configuration ............................................................................................................... 3–26
PLL Configuration ......................................................................................................................... 3–26
Example Design .............................................................................................................................. 3–27
Constraints ...................................................................................................................................... 3–29
Altera Corporation
MegaCore Version 9.1
iii
Contents
Parameters ............................................................................................................................................
Memory ............................................................................................................................................
Board & Controller .........................................................................................................................
Project Settings ................................................................................................................................
MegaCore Verification ........................................................................................................................
Simulation Environment ...............................................................................................................
Hardware Testing ...........................................................................................................................
3–29
3–30
3–31
3–33
3–34
3–34
3–34
Additional Information
Revision History ............................................................................................................................... Info–i
How to Contact Altera ..................................................................................................................... Info–i
Typographic Conventions .............................................................................................................. Info–ii
iv
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
Altera Corporation
1. About This MegaCore
Function
Release
Information
Table 1–1
provides information about this release of the Altera
®
QDRII
SRAM Controller MegaCore
®
function.
Table 1–1. Release Information
Item
Version
Release Date
Ordering Code
Product ID
Vendor ID
Description
9.1
November 2009
IP-SRAM/QDRII
00A4
6AF7
f
For more information about this release, refer to the
MegaCore IP Library
Release Notes and Errata.
Altera verifies that the current version of the Quartus
®
II software
compiles the previous version of each MegaCore function. The
MegaCore
IP Library Release Notes and Errata
report any exceptions to this
verification. Altera does not verify compilation with MegaCore function
versions older than one release.
Device Family
Support
MegaCore functions provide either full or preliminary support for target
Altera device families:
■
■
Full support
means the MegaCore function meets all functional and
timing requirements for the device family and may be used in
production designs
Preliminary support
means the MegaCore function meets all
functional requirements, but may still be undergoing timing analysis
for the device family; it may be used in production designs with
caution.
Altera Corporation
November 2009
MegaCore Version 9.1
1–1
Embedded System
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