Viterbi IP Core User Guide
Updated for Intel
®
Quartus
®
Prime Design Suite:
17.1
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Contents
Contents
1 About the Viterbi IP Core................................................................................................. 3
1.1
1.2
1.3
1.4
1.5
1.6
Intel
®
DSP IP Core Features.....................................................................................3
Viterbi IP Core Features...........................................................................................4
DSP IP Core Device Family Support........................................................................... 4
DSP IP Core Verification...........................................................................................5
Viterbi IP Core Release Information...........................................................................5
Viterbi IP Core Performance and Resource Utilization................................................... 5
2 Viterbi IP Core Getting Started........................................................................................ 9
2.1 Installing and Licensing Intel FPGA IP Cores............................................................... 9
2.1.1 Intel FPGA IP Evaluation Mode......................................................................9
2.1.2 Viterbi IP Core Intel FPGA IP Evaluation Mode Timeout Behavior......................12
2.2 IP Catalog and Parameter Editor............................................................................. 12
2.3 Generating IP Cores (Intel Quartus Prime Pro Edition)................................................14
2.3.1 IP Core Generation Output (Intel Quartus Prime Pro Edition)...........................15
2.4 Simulating Intel FPGA IP Cores............................................................................... 18
2.5 DSP Builder for Intel FPGAs Design Flow.................................................................. 18
3 Viterbi IP Core Functional Description........................................................................... 19
3.1 Decoder...............................................................................................................19
3.2 Convolutional Encoder........................................................................................... 19
3.3 Trellis Coded Modulation........................................................................................ 19
3.3.1 Half-Rate Convolutional Codes.................................................................... 20
3.3.2 Trellis Decoder..........................................................................................22
3.3.3 About Converting Received Signals..............................................................23
3.3.4 Trellis Termination.....................................................................................25
3.3.5 Trellis Initialization ................................................................................... 25
3.4 Viterbi IP Core Parameters..................................................................................... 25
3.4.1 Architecture............................................................................................. 25
3.4.2 Code Sets................................................................................................ 28
3.4.3 Viterbi Parameters.................................................................................... 28
3.4.4 Test Data................................................................................................. 30
3.5 Viterbi IP Core Interfaces and Signals...................................................................... 31
3.5.1 Avalon-ST Interfaces in DSP IP Cores.......................................................... 31
3.5.2 Global Signals.......................................................................................... 32
3.5.3 Avalon-ST Sink Signals.............................................................................. 32
3.5.4 Avalon Source-ST Signals...........................................................................33
3.5.5 Configuration Signals.................................................................................34
3.5.6 Status Signals.......................................................................................... 34
3.5.7 Viterbi IP Core Timing Diagrams................................................................. 35
A Viterbi IP Core User Guide Document Archives.............................................................. 37
5 Document Revision History............................................................................................ 38
Viterbi IP Core User Guide
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UG-VITERBI | 2017.11.06
1 About the Viterbi IP Core
Related Links
•
Introduction to Intel FPGA IP Cores
Provides general information about all Intel FPGA IP cores, including
parameterizing, generating, upgrading, and simulating IP cores.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP
version upgrades.
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
Viterbi IP Core User Guide Document Archives
on page 37
Provides a list of user guides for previous versions of the Viterbi IP core.
•
•
•
1.1 Intel
®
DSP IP Core Features
•
•
•
•
Avalon
®
Streaming (Avalon-ST) interfaces
DSP Builder for Intel
®
FPGAs ready
Testbenches to verify the IP core
IP functional simulation models for use in Intel-supported VHDL and Verilog HDL
simulators
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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9001:2008
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1 About the Viterbi IP Core
UG-VITERBI | 2017.11.06
1.2 Viterbi IP Core Features
•
High-speed parallel architecture:
—
—
—
•
—
—
—
•
—
—
—
—
—
•
•
Performance of over 250 megabits per second (Mbps)
Fully parallel operation
Optimized block decoding and continuous decoding
Configurable number of add compare and select (ACS) units
Memory-based architecture
Wide range of performance; wide range of logic area
Number of coded bits
Constraint length
Number of soft bits
Traceback length
Polynomial for each coded bit
Low to medium-speed, hybrid architecture:
Fully parameterized Viterbi decoder, including:
Variable constraint length
Trellis coded modulation (TCM) option
1.3 DSP IP Core Device Family Support
Intel offers the following device support levels for Intel FPGA IP cores:
•
Advance support—the IP core is available for simulation and compilation for this
device family. FPGA programming file (
.pof
) support is not available for Quartus
Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be
guaranteed. Timing models include initial engineering estimates of delays based
on early post-layout information. The timing models are subject to change as
silicon testing improves the correlation between the actual silicon and the timing
models. You can use this IP core for system architecture and resource utilization
studies, simulation, pinout, system latency assessments, basic timing assessments
(pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O
standards tradeoffs).
Preliminary support—Intel verifies the IP core with preliminary timing models for
this device family. The IP core meets all functional requirements, but might still be
undergoing timing analysis for the device family. You can use it in production
designs with caution.
Final support—Intel verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family. You can use it in production designs.
•
•
Table 1.
DSP IP Core Device Family Support
Device Family
Support
Final
Final
continued...
Arria
®
II GX
Arria II GZ
Viterbi IP Core User Guide
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1 About the Viterbi IP Core
UG-VITERBI | 2017.11.06
Device Family
Arria V
Intel Arria 10
Cyclone
®
IV
Cyclone V
Intel Cyclone 10
Intel MAX
®
10 FPGA
Stratix
®
IV GT
Stratix IV GX/E
Stratix V
Intel Stratix 10
Other device families
Final
Final
Final
Final
Final
Final
Final
Final
Final
Advance
No support
Support
1.4 DSP IP Core Verification
Before releasing a version of an IP core, Intel runs comprehensive regression tests to
verify its quality and correctness. Intel generates custom variations of the IP core to
exercise the various parameter options and thoroughly simulates the resulting
simulation models with the results verified against master simulation models.
1.5 Viterbi IP Core Release Information
Use the release information when licensing the IP core.
Table 2.
Release Information
Item
Version
Release Date
Ordering Code
Description
17.1
November 2017
IP-VITERBI/HS (parallel architecture) IP-VITERBI/SS (hybrid
architecture)
Intel verifies that the current version of the Quartus Prime software compiles the
previous version of each IP core. Intel does not verify that the Quartus Prime software
compiles IP core versions older than the previous version. The
Intel FPGA IP Release
Notes
lists any exceptions.
Related Links
•
•
Intel FPGA IP Release Notes
Errata for Viterbi IP core in the Knowledge Base
1.6 Viterbi IP Core Performance and Resource Utilization
This typical expected performance uses different architectures and constraint length,
L, combinations, and ACS units, A, and the Quartus Prime software. Performance
largely depends on constraint length, L.
Viterbi IP Core User Guide
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