NXH5104
4 Mbit Serial SPI EEPROM
Rev. 6.2 — 16 May 2017
Product data sheet
COMPANY PUBLIC
1
General description
The NXP NXH5104 is a 4 Mbit serial electrically erasable and programmable read-only
memory (EEPROM). It provides byte level and page level serial EEPROM functions,
sector level protection and power-down functions. The device has been developed for
low-power low-voltage applications and is provided with a Serial Peripheral Interface
(SPI) compatible interface.
2
Features and benefits
•
Compact Wafer Level Chip Scale Package (WLCSP) package
2
• –
7.8 mm , 380 μm thick
–
13 bumps with 400 μm pitch
•
Integrated Power Management Unit (PMU)
• –
V
DD
supply range 1.0 V to 2.0 V
–
V
DD(IO)
supply range: V
DD
to 2.6 V
–
Direct operation from ZnAir, NiMH, Silver-Zinc batteries
–
Active peak current limiting
•
Low current consumption
• –
Average power down current < 5 μA
–
Average read current 0.6 mA (V
DD
= V
DD(IO)
= 1.8 V, F
SPI
=5 MHz)
–
Average write current 0.7 mA (V
DD
= V
DD(IO)
= 1.8 V, F
SPI
= 5 MHz)
•
Low-power CMOS technology
•
Auxiliary supply voltage enabling direct LED drive
•
Self-timed program cycle
• –
256 byte page write buffer
–
Partial page write allowed
•
Write Protect
• –
Quarter, half or entire memory array
•
Serial Peripheral Interface (SPI)
• –
Speed up to 5 MHz for 1.2 V signaling level
–
Speed up to 10 MHz for 1.8 V signaling level
–
SPI Mode 0 (0,0) and 3 (1,1) support
–
SPI 3-wire support for SPI mode 0
•
Fixed High Supply mode for faster start-up
•
Space-saving 2.80 mm × 2.74 mm Wafer Level Chip Scale Package (WLCSP)
•
Highly integrated: 1 external cap
•
High Reliability
• –
10-year data retention
–
500 000 program cycles
–
Wear-out management
NXP Semiconductors
4 Mbit Serial SPI EEPROM
•
•
•
•
Operating temperature −20 °C to +85 °C
Support for different supply configurations
Device ID and Unique ID
Pb-free and RoHS compliant
NXH5104
3
Ordering information
Package
Name
Description
wafer level chip-scale package; 13 bumps;
2.74 mm × 2.80 mm × 0.38 mm
Table 1. Ordering information
Type number
NXH5104UK/A1
Version
SOT1461-1
WLCSP13
4
Block diagram
V
DD(IO)
V
DD
I/O supply
CS
SCK
SI
SO
HOLD
SPI
SLAVE
NXH5104
+ 8 x 4 kB RESERVED AREA: REDUNDANCY,
UNIQUE ID, TYPE ID, NON-VOLATILE SETTINGS
WAKE
(I/O at V
DD
)
DC-to-DC
CONVERTERS
64 kB SECTOR
64 kB SECTOR
V
AUX
V
DD(EE)
internal
supplies
64 kB SECTOR
4 Mbit user area
64 kB SECTOR
WP
EEPROM
CONTROLLER
64 kB SECTOR
64 kB SECTOR
64 kB SECTOR
64 kB SECTOR
WRS
V
SS
aaa-010722
Figure 1. Block diagram
NXH5104
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 6.2 — 16 May 2017
2 / 38
NXP Semiconductors
4 Mbit Serial SPI EEPROM
NXH5104
5
Pinning information
5.1 Pinning
SI
F
SO
E
WP
D
HOLD
C
SCK
B
CS
A
1
2
3
4
5
6
WRS
WAKE
V
DD
V
DD(EE)
V
SS
V
DD(IO)
V
AUX
aaa-010723
Figure 2. NXH5104 13 bump SPI package configuration (bottom view)
5.2 Pin description
Table 2. Bump allocation table
Bump Symbol
SUPPLY
B6
V
DD
Type
PWR
Description
primary supply input. The V
DD
pin is used to supply the
source voltage to the device. Operations at invalid V
DD
voltages may produce spurious results and should not be
attempted.
input/output supply input. The V
DD(IO)
pin is used to
supply the IO voltage to the device and hence defines the
signaling voltage of the SPI slave interface. The voltage
level of V
DD(IO)
must be equal or higher than V
DD
.
EEPROM array supply output. In Wide Range Supply
mode, this pin requires a 470 nF decoupling capacitor. In
Fixed High Supply (FHS) mode, this pin must be pulled
HIGH with a 1 MΩ resistor to V
DD
.
auxiliary supply output. This pin provides a configurable
voltage source for supplying other devices.
Section 6.3
describes this functionality. A separate Application Note
(Ref.
2)
provides more detailed usage information.
analog/digital ground. Connect to the system GND.
E6
V
DD(IO)
PWR
C6
V
DD(EE)
PWR
F6
V
AUX
PWR
GROUND
D6
V
SS
GND
NXH5104
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 6.2 — 16 May 2017
3 / 38
NXP Semiconductors
4 Mbit Serial SPI EEPROM
Bump Symbol
CONFIGURATION
D1
WP
DI
write-protect pin. This pin is used to prevent inadvertent
writes to the EEPROM array. When connected to GND, the
device is write protected. When connected to V
DD(IO)
, the
device is not write protected.
wide-range supply pin. This pin configures the supply mode
of the device. When connected to V
DD(IO)
, the chosen
supply mode is the Wide Range Supply mode. When
connected to GND, the chosen supply mode is the Fixed
High Supply mode. In this latter mode, a higher minimum
voltage is required on V
DD
, as described in
Section 6.4.
wake-up/power-down control input. To disable this
functionality, the WAKE pin must be connected to GND.
The SPI slave chip select input can then be used to
wake up the device. To enable the WAKE functionality,
the WAKE pin must be actively driven and may not be
left unconnected nor floating. The input voltage level is
referenced to V
DD
.
SPI slave chip select. Asserting the CS pin selects the
device. When the device is deselected, the SPI SO output
pin is in a HIGH impedance state. Commands issued to
the device are not accepted.A HIGH to LOW transition on
the CS pin initiates an operation, a LOW to HIGH transition
ends an operation.For communication, the signaling level
is referenced to V
DD(IO)
For waking up the device, the input
level is referenced to V
DD
.
SPI slave serial data output. The SO pin is used to shift
data out from the device. Data on the SO pin is always
clocked out on the falling edge of SCK. The SO pin is in a
high impedance state whenever the device is not selected.
The signaling level is referenced to V
DD(IO)
.For EMI, it is
required to pull-up the SO line at some place in the system:
either the SPI master has an internal weak pull-up, either
an external pull-up resistor is required.
SPI slave serial data input. The SI pin is used the shift
opcodes, addresses and data into the device and latched
on the rising edge of SCK. The signaling level is referenced
to V
DD(IO)
.
SPI clock input.
SPI HOLD. The HOLD pin can be used to pause an on-
going SPI transaction. More information on usage can be
found in
Section 6.1.1.
The signaling level is referenced
to V
DD(IO)
. To disable this functionality, the HOLD pin must
be connected to V
DD(IO)
.
NXH5104
Type
Description
A2
WRS
DI
CONTROL
A6
WAKE
DI
SPI
A1
CS
DI
E1
SO
DO
F1
SI
DI
B1
C1
SCK
HOLD
DI
DI
NXH5104
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 6.2 — 16 May 2017
4 / 38
NXP Semiconductors
4 Mbit Serial SPI EEPROM
NXH5104
6
Functional description
6.1 SPI interface
The NXP NXH5104 acts as a slave device on the Serial Peripheral Interface (SPI) bus.
It supports mode 0 (0,0) and mode 3 (1,1) transfers at standard clock speeds up to
5 MHz. It also supports high-speed operation up to 10 MHz when V
DD(IO)
exceeds 1.8 V.
Incoming data on the SI pin is latched on the rising edge of SCK. Outgoing data output
on the SO pin is output on the falling edge of SCK. A leading or trailing falling edge of
SCK is discarded.
CS
SCK
SI
X
7
MSB
6
5
4
3
2
1
0
LSB
X
SO
high impedance
7
6
5
4
3
2
1
0
X
aaa-010725
Figure 3. SPI mode 0/3
Transactions are byte-oriented, counting an integer multiple of 8-bit words, whereby the
Most Significant Bit (MSB) is transmitted first, Least Significant Bit (LSB) last. The master
initiates a transaction by asserting CS low and terminates it by de-asserting CS high,
even if it is a single-byte command.
The command byte is the first byte transmitted by the master and received by the slave
on the SI line after asserting low the CS pin.
6.1.1 SPI transaction hold
A HOLD input is provided as an extension to the SPI interface. It enables the host to
suspend an ongoing transaction such as performing a high priority transaction with
another slave device.
While HOLD is asserted low, the device releases the SO line to a high impedance state
and discards any transitions on SCK and SI lines. The CS line however, must remain
asserted. The suspended transaction resumes when the HOLD input is de-asserted high.
CS
HOLD
SCK
SI
SO
0
0
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
7
suspended
X
X
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
X
X
ongoing transaction
2
nd
part of transaction
aaa-010726
Figure 4. SPI transaction hold
NXH5104
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 6.2 — 16 May 2017
5 / 38
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