S70FS01GS
1-Gb (128 MB), 1.8 V FS-S Flash
Features
■
SPI with Multi-I/O
❐
SPI Clock polarity and phase modes 0 and 3
❐
DDR
❐
Extended Addressing: 24- or 32-bit address options
❐
Serial Command subset and footprint compatible with
S25FL1-K, S25FL-P, and S25FL-S SPI families
❐
Multi I/O Command subset and footprint compatible with
S25FL-P, S25FL1-K, and S25FL-S SPI families
Read
❐
Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O
❐
Modes: Burst Wrap, Quad Peripheral Interface (QPI)
❐
Serial Flash Discoverable Parameters (SFDP) and Common
Flash Interface (CFI), for configuration information.
Program
❐
256 or 512 Bytes Page Programming buffer
❐
Program suspend and resume
❐
Automatic Error Correcting Code (ECC) – internal hardware
ECC with single bit error correction
Erase
❐
Hybrid sector option
• Physical set of eight 4 KB sectors and one 224 KB sector
at the top or bottom of address space with all remaining
sectors of 256 KB
❐
Uniform sector option
• Physical uniform 256 KB blocks
❐
Erase suspend and resume
❐
Erase status evaluation
❐
100,000 Program-Erase Cycles on any sector, minimum
❐
20 year data retention, minimum
■
■
Security Features
❐
OTP array of 1024 Bytes
❐
Block Protection:
• Status Register bits to control protection against program
or erase of a contiguous range of sectors.
• Hardware and software control options
❐
Advanced Sector Protection (ASP)
• Individual sector protection controlled by boot code or
password
• Option for password control of read access
Technology
❐
Cypress 65 nm MirrorBit Technology with Eclipse Architec-
ture
Single Supply Voltage with CMOS I/O
❐
1.7V to 2.0V
Temperature Range
❐
Industrial (40 °C to +85 °C)
❐
Industrial Plus (40 °C to +105 °C)
❐
Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
❐
Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
❐
Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
❐
16-lead SOIC 300 mil
❐
BGA-24 6
8 mm
• 5
5 ball footprint
■
■
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 002-03833 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 23, 2018
S70FS01GS
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
WP#/IO2
RESET#/IO3
Data Path
I/O
X Decoders
SRAM
MirrorBit Array
Y Decoders
Data Latch
Control
Logic
Performance Summary
Maximum Read Rates
Command
Read
Fast Read
Dual Read
Quad Read
DDR Quad I/O Read
Typical Program and Erase Rates
Operation
Page Programming (256-bytes page buffer)
Page Programming (512-bytes page buffer)
4-KB Physical Sector Erase (Hybrid Sector Option)
256-KB Sector Erase (Uniform Logical Sector Option)
Typical Current Consumption,
40°C
to +85°C
Operation
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 133 MHz
Quad DDR Read 80 MHz
Program
Erase
Standby
Deep Power Down (DPD)
Current (mA)
10
20
60
70
60
60
0.07
0.006
KBps
712
1080
28
250
Clock Rate (MHz)
50
133
133
133
80
MBps
6.25
16.5
33
66
80
Document Number: 002-03833 Rev. *D
Page 2 of 140
S70FS01GS
Contents
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
4.5
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
7.
7.1
7.2
7.3
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
4
7
8
7.4
7.5
7.6
7.7
8.
8.1
8.2
8.3
8.4
8.5
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
JEDEC JESD216 Serial Flash Discoverable
Parameters (SFDP) Space ........................................... 41
OTP Address Space ..................................................... 42
Error Correction Code (ECC)........................................ 43
Registers....................................................................... 44
Data Protection
........................................................... 60
Secure Silicon Region (OTP)........................................ 60
Write Enable Command................................................ 61
Block Protection ............................................................ 61
Advanced Sector Protection ......................................... 63
Recommended Protection Process .............................. 68
Commands
.................................................................. 69
Command Set Summary............................................... 70
Identification Commands .............................................. 76
Register Access Commands......................................... 78
Read Memory Array Commands .................................. 87
Program Flash Array Commands ................................. 94
Erase Flash Array Commands...................................... 96
One Time Program Array Commands ........................ 103
Advanced Sector Protection Commands .................... 104
Reset Commands ....................................................... 109
DPD Commands ......................................................... 111
Signal Descriptions
..................................................... 9
Input/Output Summary................................................... 9
Multiple Input / Output (MIO)........................................ 10
Serial Clock (SCK) ....................................................... 10
Chip Select (CS#) ........................................................ 10
Serial Input (SI) / IO0 ................................................... 10
Serial Output (SO) / IO1............................................... 10
Write Protect (WP#) / IO2 ............................................ 10
IO3 / RESET# .............................................................. 11
Voltage Supply (V
CC
)................................................... 11
Supply and Signal Ground (V
SS
) ................................. 11
Not Connected (NC) .................................................... 11
Reserved for Future Use (RFU)................................... 11
Do Not Use (DNU) ....................................................... 11
Block Diagrams............................................................ 12
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Latchup Characteristics ...............................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics. .............................................
14
14
15
18
22
22
23
23
23
23
24
26
29
29
29
30
32
35
10. Data Integrity
............................................................. 113
10.1 Erase Endurance ........................................................ 113
10.2 Data Retention ............................................................ 113
11.
Embedded Algorithm Performance Tables.............
114
12. Software Interface Reference
.................................. 115
12.1 Serial Flash Discoverable Parameters
(SFDP) Address Map.................................................. 115
12.2 Device ID and Common Flash Interface
(ID-CFI) Address Map................................................. 118
12.3 Initial Delivery State .................................................... 133
12.4 FS01GS Behavior and Software Modifications........... 134
13. Ordering Information
................................................ 136
13.1 Ordering Part Number................................................. 136
14. Revision History........................................................
138
Document History Page ................................................... 138
Sales, Solutions, and Legal Information ........................ 140
Worldwide Sales and Design Support .........................140
Products ......................................................................140
PSoC® Solutions ........................................................140
Cypress Developer Community ...................................140
Technical Support .......................................................140
Physical Interface
...................................................... 37
Connection Diagrams .................................................. 37
Physical Diagrams ....................................................... 38
Address Space Maps.................................................
Overview ......................................................................
Flash Memory Array.....................................................
ID-CFI Address Space .................................................
40
40
40
41
Document Number: 002-03833 Rev. *D
Page 3 of 140
S70FS01GS
1. Overview
1.1 General Description
The Cypress FS-S Family devices are Flash non-volatile memory products using:
■
■
■
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
The FS-S Family connects to a host system via a SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is
supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) or QPI, also known as Quad Peripheral
Interface (QPI) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, there are DDR read
commands for QIO and QPI that transfer address and read data on both edges of the clock.
The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512-bytes to be programmed in one operation,
resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from Flash memory is often called Execute-In-Place or XIP. By using FS-S Family devices at the higher
clock rates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel
interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FS-S Family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal
for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
The S70FS01GS device is a dual die stack of two FS512S die.
1.2 Migration Notes
1.2.1 Features Comparison
The FS-S Family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families. However, the
power supply and interface voltages are nominal 1.8V.
Table 1. Cypress SPI Families Comparison
Parameter
Technology Node
Architecture
Release DatWe
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
Sector Erase Rate (typ.)
Page Programming Rate (typ.)
FS-S
65nm
MirrorBit
®
Eclipse™
2H2015
1Gb
x1, x2, x4
1.7V - 2.0V
6 MBps (50MHz)
16.5 MBps (133MHz)
33 MBps (133MHz)
66 MBps (133MHz)
80 MBps (80MHz)
256B / 512B
256 KB
4 KB (option)
500 KBps
0.71 MBps (256B)
1.08 MBps (512B)
FL-S
65nm
MirrorBit
®
Eclipse™
2H2011
1GB
x1, x2, x4
2.7V - 3.6V / 1.65V - 3.6V V
IO
6MBps (50MHz)
17MBps (133MHz)
26MBps (104MHz)
52MBps (104MHz)
80MBps (80MHz)
256B / 512B
256 KB
4 KB (option)
500 KBps
1.0 MBps (256B)
1.5 MBps (512B)
Notes
1. Only 128Mb/256Mb density FL-S devices have 4 KB parameter sector option.
2. 512Mb/1Gb FL-S devices support 256 KB sector only.
3. Refer to individual datasheets for further details.
Document Number: 002-03833 Rev. *D
Page 4 of 140
S70FS01GS
Table 1. Cypress SPI Families Comparison
(Continued)
Parameter
OTP
Advanced Sector Protection
Auto Boot Mode
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
FS-S
1024B
Yes
No
Yes
Yes
-40°C to +85°C / +105°C / +125°C
FL-S
1024B
Yes
Yes
Yes
Yes
-40°C to +85°C / +105°C
Notes
1. Only 128Mb/256Mb density FL-S devices have 4 KB parameter sector option.
2. 512Mb/1Gb FL-S devices support 256 KB sector only.
3. Refer to individual datasheets for further details.
1.2.2 Known Differences from Prior Generations
1.2.2.1
Error Reporting
The FS-S and FL-S families have error reporting status bits for program and erase operations. These can be set when there is an
internal failure to program or erase, or when there is an attempt to program or erase a protected sector. In these cases the program
or erase operation did not complete as requested by the command. The P_ERR or E_ERR bits and the WIP bit will be set to and
remain 1 in SR1V. The clear status register command must be sent to clear the errors and return the device to standby state.
1.2.2.2
Secure Silicon Region (OTP)
The FS-S size and format (address map) of the One Time Program area is different from FL-K and FL-P generations. The method
for protecting each portion of the OTP area is different. For additional details see
Section 8.1 Secure Silicon Region (OTP)
on page 60.
1.2.2.3
Configuration Register Freeze Bit
The configuration register-1 Freeze Bit CR1V[0], locks the state of the Block Protection bits (SR1NV[4:2] & SR1V[4:2]), TBPARM_O
bit (CR1NV[2]), and TBPROT_O bit (CR1NV[5]), as in prior generations. In the FS-S and FL-S families the Freeze Bit also locks the
state of the configuration register-1 BPNV_O bit (CR1NV[3]), and the Secure Silicon Region (OTP) area.
1.2.2.4
Sector Erase Commands
The command for erasing a 4 KB sector is supported only for use on 4 KB parameter sectors at the top or bottom of the FS-S device
address space.
The command for erasing an 8 KB area (two 4 KB sectors) is not supported.
The command for erasing a 32 KB area (eight 4 KB sectors) is not supported.
1.2.2.5
Deep Power Down (DPD)
The DPD function is supported in the FS-S family devices.
1.2.2.6
WRR Single Register Write
In some legacy SPI devices, a Write Registers (WRR) command with only one data byte would update Status Register 1 and clear
some bits in Configuration Register 1, including the Quad Mode bit. This could result in unintended exit from Quad Mode. The FS-S
Family only updates Status Register 1 when a single data byte is provided. The Configuration Register 1 is not modified in this case.
1.2.2.7
Hold Input Not Supported
In some legacy SPI devices, the IO3 input has an alternate function as a HOLD# input used to pause information transfer without
stopping the serial clock. This function is not supported in the FS-S family.
Document Number: 002-03833 Rev. *D
Page 5 of 140
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