AT25DF041B
4-Mbit, 1.65V Minimum
SPI Serial Flash Memory with Dual-I/O Support
Features
Single 1.65V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual-I/O Operation
104MHz Maximum Operating Frequency
Clock-to-Output (t
V
) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Small (256-Byte) Page Erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Dual-Input Byte/Page Program (1 to 256 Bytes)
Sequential Program Mode Capability
Fast Program and Erase Times
1.25ms Typical Page Program (256 Bytes) Time
35ms Typical 4-Kbyte Block Erase Time
250ms Typical 32-Kbyte Block Erase Time
450ms Typical 64-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
200nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
4.5mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
8-lead TSSOP Package
8-ball WLCSP (3 x 2 x 3 ball matrix)
DS-25DF041B–040E–2/2017
1.
Description
The Adesto
®
AT25DF041B is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer
based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DF041B, with its page erase granularity it is ideal for data storage as well, eliminating the
need for additional data storage devices.
The erase block sizes of the AT25DF041B have been optimized to meet the needs of today's code and data storage applications.
By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules
and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that
occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device
density.
The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as
unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the AT25DF041B supports read, program, and erase operations with a
wide supply voltage range of 1.65V to 3.6V. No separate voltage is required for programming and erasing.
2.
Pin Descriptions and Pinouts
Pin Descriptions
Name and Function
CHIP SELECT:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected, data
will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such
as a program or erase cycle, the device will not enter the standby mode until the completion of
the operation.
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used to control the flow
of data to and from the device. Command, address, and input data present on the SI pin is
always latched in on the rising edge of SCK, while output data on the SO pin is always clocked
out on the falling edge of SCK.
SERIAL INPUT:
The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on the
rising edge of SCK.
Asserted
State
Type
Table 2-1.
Symbol
CS
Low
Input
SCK
-
Input
SI (I/O
0
)
With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O
0
) in conjunction
with other pins to allow two bits of data on (I/O
1-0
) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SI (I/O
0
) pin will be referenced as the SI
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O
0.
Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).
-
Input/
Output
AT25DF041B
DS-25DF041B–040E–2/2017
2
Table 2-1.
Symbol
Pin Descriptions (Continued)
Name and Function
SERIAL OUTPUT:
The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O
1
) in conjunction
with other pins to allow two bits of data on (I/O
1-0
) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SO (I/O
1
) pin will be referenced as the
SO pin unless specifically addressing the Dual-I/O modes in which case it ise referenced as I/O
1.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT:
The WP pin controls the hardware locking feature of the device. Please refer
to
“Protection Commands and Features” on page 17
for more details on protection features and
the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
CC
whenever possible.
HOLD:
The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
-
Input/
Output
Asserted
State
Type
SO (I/O
1
)
WP
Low
Input
HOLD
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold” on page 35
for additional details on the Hold operation.The HOLD pin is internally
pulled-high and may be left floating if the Hold function will not be used. However, it is
recommended that the HOLD pin also be externally connected to V
CC
whenever possible.
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
GROUND:
The ground reference for the power supply. GND should be connected to the system
ground.
Low
Input
V
CC
GND
-
-
Power
Power
Table 2-2.
Pinouts
Figure 2-3. 8-UDFN (Top View)
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2-1. 8-SOIC Top View
CS
SO
WP
GND
1
2
3
4
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2-2. 8-TSSOP Top View
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2-4. 8-ball WLCSP (Bottom View)
CS
GND
SO
SI
WP
SCK
HOLD
Vcc
AT25DF041B
DS-25DF041B–040E–2/2017
3
3.
Block Diagram
Figure 3-1. Block Diagram
AT25DF041B
DS-25DF041B–040E–2/2017
4
4.
Memory Array
To provide the greatest flexibility, the memory array of the AT25DF041B can be erased in three levels of granularity:
sectors, blocks and pages. There is also a full chip erase. The size of the erase blocks is optimized for both code and
data storage applications, allowing both code and data segments to reside in their own erase regions. The erase
operations can be performed at the chip, sector, block, or page level.
Program operations to the device can be done at the full page level or at the byte level (a variable number of bytes, from
1byte to 256 bytes per page). The Memory Architecture Diagram illustrates the breakdown of each erase level.
Figure 4-1. Memory Architecture Diagram
Block Erase Detail
Internal Sectoring for
Sector Protection
Function
64K
32KB
Block Erase
Block Erase
(D8h Command) (52h Command)
Page Erase Detail / Page Program Detail
(81h Command)
/
4KB
Block Erase
(20h Command)
Block Address
Range
256 Byte Page
(02h Command)
1-256 Byte Page
Page Address
Range
16KB
(Sector 10)
8KB
(Sector 9)
8KB
(Sector 8)
32KB
64KB
32KB
(Sector 7)
32KB
32KB
64KB
(Sector 6)
64KB
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
•••
07F F F F h
07E F F F h
07DF F F h
07CF F F h
07BF F F h
07AF F F h
079F F F h
078F F F h
077F F F h
076F F F h
075F F F h
074F F F h
073F F F h
072F F F h
071F F F h
070F F F h
06F F F F h
06E F F F h
06DF F F h
06CF F F h
06BF F F h
06AF F F h
069F F F h
068F F F h
067F F F h
066F F F h
065F F F h
064F F F h
063F F F h
062F F F h
061F F F h
060F F F h
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
07F 000h
07E 000h
07D000h
07C000h
07B000h
07A000h
079000h
078000h
077000h
076000h
075000h
074000h
073000h
072000h
071000h
070000h
06F 000h
06E 000h
06D000h
06C000h
06B000h
06A000h
069000h
068000h
067000h
066000h
065000h
064000h
063000h
062000h
061000h
060000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
•••
07F F F F h
07F E F F h
07F DF F h
07F CF F h
07F BF F h
07F AF F h
07F 9F F h
07F 8F F h
07F 7F F h
07F 6F F h
07F 5F F h
07F 4F F h
07F 3F F h
07F 2F F h
07F 1F F h
07F 0F F h
07E F F F h
07E E F F h
07E DF F h
07E CF F h
07E BF F h
07E AF F h
07E 9F F h
07E 8F F h
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
07F F 00h
07F E 00h
07F D00h
07F C00h
07F B00h
07F A00h
07F 900h
07F 800h
07F 700h
07F 600h
07F 500h
07F 400h
07F 300h
07F 200h
07F 100h
07F 000h
07E F 00h
07E E 00h
07E D00h
07E C00h
07E B00h
07E A00h
07E 900h
07E 800h
32KB
64KB
(Sector 0)
64KB
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
00F F F F h
00E F F F h
00DF F F h
00CF F F h
00BF F F h
00AF F F h
009F F F h
008F F F h
007F F F h
006F F F h
005F F F h
004F F F h
003F F F h
002F F F h
001F F F h
000F F F h
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00F 000h
00E 000h
00D000h
00C000h
00B000h
00A000h
009000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
0017F F h
0016F F h
0015F F h
0014F F h
0013F F h
0012F F h
0011F F h
0010F F h
000F F F h
000E F F h
000DF F h
000CF F h
000BF F h
000AF F h
0009F F h
0008F F h
0007F F h
0006F F h
0005F F h
0004F F h
0003F F h
0002F F h
0001F F h
0000F F h
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
001700h
001600h
001500h
001400h
001300h
001200h
001100h
001000h
000F 00h
000E 00h
000D00h
000C00h
000B00h
000A00h
000900h
000800h
000700h
000600h
000500h
000400h
000300h
000200h
000100h
000000h
•••
•••
•••
AT25DF041B
DS-25DF041B–040E–2/2017
5
Automotive Electronics
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