AT25DF041B-SSHN-B datasheet, PDF

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AT25DF041B-SSHN-B: DescriptionNOR Flash 8-SOIC-N, IND TEMP, 1.65V, T&R; Categorystorage storage; File Size3MB，53 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT25DF041B-SSHN-B Overview

NOR Flash 8-SOIC-N, IND TEMP, 1.65V, T&R

AT25DF041B-SSHN-B Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Adesto Technologies
package instruction	SOP,
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	13 weeks
Maximum clock frequency (fCLK)	104 MHz
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	4.925 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	1
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX1
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
Programming voltage	1.8 V
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
type	NOR TYPE
width	3.9 mm
Base Number Matches	1

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AT25DF041B

4-Mbit, 1.65V Minimum

SPI Serial Flash Memory with Dual-I/O Support

Features



Single 1.65V - 3.6V Supply



Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 and 3

Supports Dual-I/O Operation



104MHz Maximum Operating Frequency



Clock-to-Output (t

) of 6 ns



Flexible, Optimized Erase Architecture for Code + Data Storage Applications



Small (256-Byte) Page Erase



Uniform 4-Kbyte Block Erase



Uniform 32-Kbyte Block Erase



Uniform 64-Kbyte Block Erase



Full Chip Erase



Hardware Controlled Locking of Protected Sectors via WP Pin



128-byte, One-Time Programmable (OTP) Security Register

64 bytes factory programmed with a unique identifier

64 bytes user programmable



Flexible Programming



Byte/Page Program (1 to 256 Bytes)



Dual-Input Byte/Page Program (1 to 256 Bytes)



Sequential Program Mode Capability



Fast Program and Erase Times



1.25ms Typical Page Program (256 Bytes) Time



35ms Typical 4-Kbyte Block Erase Time



250ms Typical 32-Kbyte Block Erase Time



450ms Typical 64-Kbyte Block Erase Time



Automatic Checking and Reporting of Erase/Program Failures



Software Controlled Reset



JEDEC Standard Manufacturer and Device ID Read Methodology



Low Power Dissipation

200nA Ultra Deep Power Down current (Typical)

5µA Deep Power-Down Current (Typical)

25uA Standby current (Typical)

4.5mA Active Read Current (Typical)



Endurance: 100,000 Program/Erase Cycles



Data Retention: 20 Years



Complies with Full Industrial Temperature Range



Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options



8-lead SOIC (150-mil)

8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)

8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)

8-lead TSSOP Package

8-ball WLCSP (3 x 2 x 3 ball matrix)

DS-25DF041B–040E–2/2017

Description

The Adesto

AT25DF041B is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer

based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The

flexible erase architecture of the AT25DF041B, with its page erase granularity it is ideal for data storage as well, eliminating the

need for additional data storage devices.

The erase block sizes of the AT25DF041B have been optimized to meet the needs of today's code and data storage applications.

By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules

and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that

occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space

efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device

density.

The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as

unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.

Specifically designed for use in many different systems, the AT25DF041B supports read, program, and erase operations with a

wide supply voltage range of 1.65V to 3.6V. No separate voltage is required for programming and erasing.

Pin Descriptions and Pinouts

Pin Descriptions

Name and Function

CHIP SELECT:

Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in standby mode (not Deep Power-Down

mode), and the SO pin will be in a high-impedance state. When the device is deselected, data

will not be accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device will not enter the standby mode until the completion of

the operation.

SERIAL CLOCK:

This pin is used to provide a clock to the device and is used to control the flow

of data to and from the device. Command, address, and input data present on the SI pin is

always latched in on the rising edge of SCK, while output data on the SO pin is always clocked

out on the falling edge of SCK.

SERIAL INPUT:

The SI pin is used to shift data into the device. The SI pin is used for all data

input including command and address sequences. Data on the SI pin is always latched in on the

rising edge of SCK.

Asserted

State

Type

Table 2-1.

Symbol

Low

Input

SCK

Input

SI (I/O

)

With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O

) in conjunction

with other pins to allow two bits of data on (I/O

1-0

) to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the SI (I/O

) pin will be referenced as the SI

pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O

Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).

Input/

Output

AT25DF041B

DS-25DF041B–040E–2/2017

AT25DF041B-SSHN-B Related Products

	AT25DF041B-SSHN-B	AT25DF041B-DWFHT	AT25DF041B-XMHN-B
Description	NOR Flash 8-SOIC-N, IND TEMP, 1.65V, T&R	NOR Flash Die in Wafer Form	NOR Flash 8-TSSOP, HIGH TEMP, 1.65V, T&R
Maker	Adesto Technologies	Adesto Technologies	Adesto Technologies
Maximum operating temperature	85 °C	+ 125 C	-
Minimum operating temperature	-40 °C	- 40 C	-
organize	4MX1	512 k x 8	-
Product Category	-	NOR flash memory	NOR flash memory
series	-	AT25DF041B	AT25DF041B
Factory packaging quantity	-	1	100

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