S29GL064N, S29GL032N
64 Mbit, 32 Mbit 3 V Page Mode
MirrorBit Flash
Distinctive Characteristics
Architectural Advantages
■
■
■
■
Single power supply operation
Manufactured on 110 nm MirrorBit process technology
Secured SiliconSector region
❐
128-word/256-byte sector for permanent, secure identifica-
tion through an 8-word/16-byte random Electronic Serial
Number, accessible through a command sequence
❐
Programmed and locked at the factory or by the customer
Flexible sector architecture
❐
64Mb (uniform sector models): One hundred twenty-eight 32
Kword (64 KB) sectors
❐
64 Mb (boot sector models): One hundred twenty-seven 32
Kword (64 KB) sectors + eight 4Kword (8KB) boot sectors
❐
32 Mb (uniform sector models): Sixty-four 32Kword (64 KB)
sectors
❐
32 Mb (boot sector models): Sixty-three 32Kword (64 KB)
sectors + eight 4Kword (8KB) boot sectors
Enhanced VersatileI/O™ Control
❐
All input levels (address, control, and DQ input levels) and
outputs are determined by voltage on V
IO
input. V
IO
range is
1.65 to V
CC
Compatibility with JEDEC standards
❐
Provides pin out and software compatibility for single-power
supply flash, and superior inadvertent write protection
100,000 erase cycles typical per sector
20-year data retention typical
■
Low power consumption
❐
25 mA typical initial read current,
1 mA typical page read current
❐
50 mA typical erase/program current
❐
1 µA typical standby mode current
Package options
❐
48-pin TSOP
❐
56-pin TSOP
❐
64-ball Fortified BGA
❐
48-ball fine-pitch BGA
■
Software and Hardware Features
■
■
■
Software features
❐
Advanced Sector Protection: offers Persistent Sector Protec-
tion and Password Sector Protection
❐
Program Suspend & Resume: read other sectors before pro-
gramming operation is completed
❐
Erase Suspend & Resume: read/program other sectors be-
fore an erase operation is completed
❐
Data# polling & toggle bits provide status
❐
CFI (Common Flash Interface) compliant: allows host system
to identify and accommodate multiple flash devices
❐
Unlock Bypass Program command reduces overall multi-
ple-word programming time
Hardware features
❐
WP#/ACC input accelerates programming time (when high
voltage is applied) for greater throughput during system pro-
duction. Protects first or last sector regardless of sector pro-
tection settings on uniform sector models
❐
Hardware reset input (RESET#) resets device
❐
Ready/Busy# output (RY/BY#) detects program or erase cy-
cle completion
■
■
■
Performance Characteristics
■
High performance
❐
90 ns access time
❐
8-word/16-byte page read buffer
❐
25 ns page read time
❐
16-word/32-byte write buffer which reduces overall program-
ming time for multiple-word updates
Cypress Semiconductor Corporation
Document Number: 001-98525 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 26, 2017
S29GL064N, S29GL032N
General Description
The S29GL-N family of devices are 3.0-Volt single-power Flash
memory manufactured using 110 nm MirrorBit technology. The
S29GL064N is a 64-Mb device organized as 4,194,304 words
or 8,388,608 bytes. The S29GL032N is a 32-Mb device
organized as 2,097,152 words or 4,194,304 bytes. Depending
on the model number, the devices have 16-bit wide data bus
only, or a 16-bit wide data bus that can also function as an 8-bit
wide data bus by using the BYTE# input. The devices can be
programmed either in the host system or in standard EPROM
programmers.
Access times as fast as 90 ns are available. Note that each
access time has a specific operating voltage range (V
CC
) as
specified in the
Product Selector Guide
and the
Ordering
Information–S29GL032N
, and
Ordering Information–
S29GL064N.
Package offerings include 48-pin TSOP, 56-pin
TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA,
depending on model number. Each device has separate chip
enable (CE#), write enable (WE#) and output enable (OE#)
controls.
Each device requires only a
single 3.0-Volt power supply
for
both read and write functions. In addition to a V
CC
input, a
high-voltage
accelerated program (ACC)
feature provides
shorter programming times through increased voltage on the
WP#/ACC or ACC input. This feature is intended to facilitate
factory throughput during system production, but may also be
used in the field if desired.
The device is entirely command set compatible with the
JEDEC
single-power-supply Flash standard.
Commands are written
to the device using standard microprocessor write timing. Write
cycles also internally latch addresses and data needed for the
programming and erase operations.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The device is fully erased when shipped from
the factory.
The
Advanced Sector Protection
features several levels of
sector protection, which can disable both the program and
erase operations in certain sectors. Persistent Sector
Protection is a method that replaces the previous 12-volt
controlled protection method. Password Sector Protection is a
highly sophisticated protection method that requires a
password before changes to certain sectors are permitted.
Device programming and erasure are initiated through
command sequences. Once a program or erase operation
begins, the host system need only poll the DQ7 (Data# Polling)
or DQ6 (toggle)
status bits
or monitor the
Ready/Busy#
(RY/BY#)
output to determine whether the operation is
complete. To facilitate programming, an
Unlock Bypass
mode
reduces command sequence overhead by requiring only two
write cycles to program data instead of four.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combination
of sectors of memory. This can be achieved in-system or via
programming equipment.
The
Erase Suspend/Erase Resume
feature allows the host
system to pause an erase operation in a given sector to read or
program any other sector and then complete the erase
operation. The
Program Suspend/Program Resume
feature
enables the host system to pause a program operation in a
given sector to read any other sector and then complete the
program operation.
The
hardware RESET# pin
terminates any operation in
progress and resets the device, after which it is then ready for a
new operation. The RESET# pin may be tied to the system
reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the
Flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels on CE# and RESET#, or
when addresses are stable for a specified period of time.
The
Write Protect (WP#)
feature protects the first or last sector
by asserting a logic low on the WP#/ACC pin or WP# pin,
depending on model number. The protected sector is still
protected even during accelerated programming.
The
Secured Silicon Sector
provides a 128-word/256-byte
area for code or data that can be permanently protected. Once
this sector is protected, no further changes within the sector can
occur.
Cypress MirrorBit flash technology combines years of Flash
memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness. The device
electrically erases all bits within a sector simultaneously via
hot-hole assisted erase. The data is programmed using hot
electron injection.
Document Number: 001-98525 Rev. *B
Page 2 of 78
S29GL064N, S29GL032N
Contents
1.
2.
3.
4.
5.
6.
7.
7.1
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
9.
10.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Product Selector Guide
............................................... 4
Block Diagram..............................................................
4
Connection Diagrams..................................................
5
Pin Description.............................................................
9
Logic Symbols
........................................................... 10
Ordering Information–S29GL032N
........................... 12
Ordering Information–S29GL064N
........................... 14
Valid Combinations ...................................................... 15
Device Bus Operations..............................................
Word/Byte Configuration..............................................
Requirements for Reading Array Data.........................
Writing Commands/Command Sequences..................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
RESET#: Hardware Reset Pin.....................................
Output Disable Mode ...................................................
Autoselect Mode ..........................................................
Advanced Sector Protection ........................................
Lock Register ...............................................................
Persistent Sector Protection ........................................
Password Sector Protection.........................................
Password and Password Protection Mode Lock Bit ....
Persistent Protection Bit Lock (PPB Lock Bit)..............
Secured Silicon Sector Flash Memory Region ............
Write Protect (WP#/ACC) ............................................
Hardware Data Protection............................................
16
16
16
17
18
18
18
18
29
30
30
31
33
33
33
34
35
35
10.9 Command Definitions.................................................... 47
10.10Write Operation Status ................................................. 52
10.11DQ7: Data# Polling....................................................... 53
10.12RY/BY#: Ready/Busy# ................................................. 54
10.13DQ6: Toggle Bit I .......................................................... 54
10.14DQ2: Toggle Bit II ......................................................... 55
10.15Reading Toggle Bits DQ6/DQ2 .................................... 55
10.16DQ5: Exceeded Timing Limits ...................................... 55
10.17DQ3: Sector Erase Timer ............................................. 55
10.18DQ1: Write-to-Buffer Abort ........................................... 56
11.
12.
13.
Absolute Maximum Ratings.......................................
57
Operating Ranges
....................................................... 58
DC Characteristics......................................................
58
14. Test Conditions
........................................................... 60
14.1 Key to Switching Waveforms ........................................ 60
15.
16.
AC Characteristics......................................................
61
Erase And Programming Performance.....................
70
17. Data Integrity
............................................................... 71
17.1 Erase Endurance .......................................................... 71
17.2 Data Retention .............................................................. 71
18. Physical Dimensions
.................................................. 72
18.1 TS048—48-Pin Standard Thin Small
Outline Package (TSOP) .............................................. 72
18.2 TS056—56-Pin Standard Thin Small
Outline Package (TSOP) .............................................. 73
18.3 VBK048—Ball Fine-pitch Ball Grid Array
(BGA) 8.15x 6.15 mm Package .................................... 74
18.4 LAA064—64-Ball Fortified Ball Grid Array
(BGA) 13 x 11 mm Package ......................................... 75
18.5 LAE064-64-Ball Fortified Ball Grid Array
(BGA) 9 x 9 mm Package ............................................. 76
19. Revision History..........................................................
77
Sales, Solutions, and Legal Information .......................... 78
Worldwide Sales and Design Support ...........................78
Products ........................................................................ 78
PSoC® Solutions .......................................................... 78
Cypress Developer Community .....................................78
Technical Support ......................................................... 78
Common Flash Memory Interface (CFI)
................... 36
Command Definitions................................................
Reading Array Data .....................................................
Reset Command ..........................................................
Autoselect Command Sequence .................................
Enter/Exit Secured Silicon Sector
Command Sequence ...................................................
Program Suspend/Program Resume
Command Sequence ...................................................
Chip Erase Command Sequence ................................
Sector Erase Command Sequence .............................
Erase Suspend/Erase Resume Commands ................
39
39
39
40
40
43
44
45
46
Document Number: 001-98525 Rev. *B
Page 3 of 78
S29GL064N, S29GL032N
1.
Product Selector Guide
S29GL064N
V
CC
= 2.7–3.6 V
V
IO
= 2.7–3.6 V
V
IO
= 1.65–3.6 V
90
90
25
25
90
110
110
110
30
30
90
90
25
25
S29GL032N
90
110
110
110
30
30
Part Number
Speed Option
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
2. Block Diagram
RY/BY#
V
CC
V
SS
Sector Switches
DQ15
–
DQ0 (A-1)
Erase Voltage
Generator
RESET#
Input/Output
Buffers
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
Y-Decoder
STB
Y-Gating
Timer
Address Latch
V
CC
Detector
X-Decoder
Cell Matrix
A
Max
**–A0
Note
**A
MAX
GL064N = A21, GL032N = A20.
Document Number: 001-98525 Rev. *B
Page 4 of 78
S29GL064N, S29GL032N
3.
Connection Diagrams
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity
may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Figure 1. 48-Pin Standard TSOP
S29GL064N, S29GL032N
(Models 03, 04 only)
S29GL064N
(Models 06, 07, V6, V7 only)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
V
IO
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
NC on S29GL032N
Document Number: 001-98525 Rev. *B
Page 5 of 78
Embedded System
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