USER’S MANUAL
ISL68201-99125DEMO1Z
Demonstration Board
The
ISL68201
is a single-phase synchronous buck PWM
controller featuring Intersil’s proprietary R4™ Technology,
which has extremely fast transient performance, accurately
regulated frequency control, and all internal compensation.
The ISL68201 supports a wide 4.5V to 24V input voltage range
and a wide 0.5V to 5.5V output range. It includes
programmable functions and telemetries for easy use and
high system flexibility using the SMBus, PMBus, or I
2
C
interface. Refer to the
ISL68201
datasheet for more details.
The
ISL99125B
is a DrMOS power stage compatible with
Intersil’s 5V PWM controllers, such as the ISL6398, ISL637x,
ISL633x, ISL636x, ISL9585x, and ISL68201. They use a DCR
sensing network and associated thermal compensation.
Light-load efficiency is supported through a dedicated FCCM
control pin. A thermally enhanced 3.5x5 QFN 24 Ld package
allows minimal overall PCB real estate.
The ISL68201-99125DEMO1Z is a 6-layer board demonstrating
a compact 13mmx13mm 16A synchronous buck converter. The
board can be used to evaluate transient performance, fault
protections, DC/AC regulations, PMBus programming, power
sequencing, margining, and other features.
The PMBus dongle (ZLUSBEVAL3Z USB-to-PMBus adapter) and
USB cable are included in the demonstration kit. Intersil’s
PowerNavigator™ evaluation software can be installed from
Intersil’s website and be used to evaluate the full PMBus
functionality of the part using a PC running Microsoft
Windows.
UG086
Rev.2.00
Nov 28, 2017
Key Features
• 16A synchronous buck converter with PMBus control
• On-board transient load with adjustable di/dt
• Configurable through resistor pins
• Cascadable PMBus connectors
• Integrated LDOs for a single rail solution
• Enable switch and power-good indicator
• All ceramics solution with SP capacitor footprint option
Target Specifications
• V
IN
= 4.75V to 14.5V
• V
OUT
= 3.3V/16A full load
• f
SW
= 500kHz
• Peak efficiency:
- 94.4% at 9A/3.3V
OUT
/12V
IN
/500kHz
- 97.1% at 6A/3.3V
OUT
/5V
IN
/400kHz
• Output regulation: 3.3V ±0.5%
• I/O capacitor rating: C
IN
- 16V; C
OUT
- 6.3V
Compact size: 13mmx13mm
• With or without PMBus, SMBus, and I
2
C capability
Ordering Information
PART NUMBER
DESCRIPTION
ISL68201-99125DEMO1Z ISL68201-99125 Demonstration Board
(Items shipped: Demonstration board,
dongle, and USB cable)
Related Literature
• For a full list of related documents, visit our website
-
ISL68201
product page
-
ISL99125B
product page
• Intersil’s
PowerNavigator
User Guide
1.0µF
VCC
7VLDO
SALERT
SCL
SDA
PGOOD
EN
IOUT
LGIN
100
VCC
PVCC
VIN
4.7µF
4.75 TO 24V
1.0µF
I C/
SMBus/
PMBus
PGOOD
EN
VCC
2
ISL99125B
FCCM
PWM
FCCM
UG
PWM
LG
BOOT
V
OUT
< 7VLDO - 1.7V
0.5V TO 5.5V
PHASE
10k
NTC
1.54k
VCC
4
NTC
0.1µF
PROG1-4
CSEN
CSRTN
VSEN
RGND
NCP18XH103J03RB
BETA = 3380
GND
FIGURE 1. ISL68201-99125DEMO1Z SIMPLIFIED SCHEMATIC
UG086 Rev.2.00
Nov 28, 2017
Page 1 of 23
ISL68201-99125DEMO1Z
FIGURE 2. DEMONSTRATION BOARD TOP VIEW
FIGURE 3. DEMONSTRATION BOARD BOTTOM VIEW
Demonstration Board
Description
The ISL68201-99125DEMO1Z provides all circuitry required to
demonstrate the key features of the ISL68201. A majority of the
features of the ISL68201 are available on this demonstration
board, such as optimal transient response with Intersil’s R4
Modulator, 8-bit programmable boot voltage levels, selectable
switching frequency in continuous conduction mode, power-good
monitor for soft-start and fault detection, over-temperature
protection, output overcurrent and short-circuit protection, and
output overvoltage protection.
Figure 1 on page 1
shows a simplified schematic diagram of the
ISL68201-99125DEMO1Z board.
Figure 6 on page 7
shows the
detailed 16A buck solution schematics, while
Figure 7 on page 8
shows the I/O connectors, auxiliary circuits and on-board
transient circuits.
Figures 8
through
33
show typical performance
data and
Figures 34
through
41
show the PCB board layout. The
default programming pins setting is shown in the lower left
corner of
Figure 6,
and the Bill of Materials (BOM) is included for
reference beginning on
page 9.
The ISL68201-99125DEMO1Z board can run by itself without a
serial bus communication. The operational configuration is fully
programmable using the programming pins (PROG1-4).
The ISL68201 however, uses the PMBus/SMBus/I
2
C protocol
and provides the flexibility for digital power management and
performance optimization before finalizing the hardware
configuration on the programming pins.
The buck regulator in the ISL68201-99125DEMO1Z board is a
single input rail design, that is, everything is biased by the input
supply (typically 12V). The resistor divider on the EN pin (R
4
and
R
12
) can set the input supply undervoltage protection level and
its hysteresis. The “ENABLE” switch is a hardware operational
control. Alternately, the serial bus ON_OFF_CONFIG and
OPERATION commands can be used for software operational
control.
Furthermore, an on-board transient load, as shown in
Figure 4 on
page 3,
with di/dt and load step amplitude is controlled by a
function generator. Because this auxiliary circuit draws more
than 10mA of current, the jumper on JP4 should be removed for
accurate efficiency measurement.
Intersil’s PowerNavigator evaluation software is compatible with
Windows operating systems and can be used to evaluate the
serial bus functionality of the ISL68201. The software and user
guide can be found at
http://www.intersil.com/powernavigator.
Quick Start Guide
Standalone Operation
1. Set the ENABLE switch to the “OFF” position.
2. Connect a power supply (off) to input connectors (J4-VIN and
J3-GND).
3. Set the input power supply voltage level (no more than 15V)
and current limiting (no more than 1A for 0A load).
4. Turn the power supply on.
5. Set the ENABLE switch to the “ON” position.
6. Increase the power supply current limit enough to support
more than the full load.
7. Apply load to the output connectors (J1-VOUT and J2-SGND).
8. Monitor the operation using an oscilloscope.
PMBus Operation
1. Connect the supplied dongle to J8.
2. Connect the USB cable from the computer to the dongle.
3. After the input supply powers up, open the PowerNavigator
evaluation software.
4. Select the detected ISL68201 device (Address - 7Fh) and
follow the instructions in the PowerNavigator user guide.
5. Monitor and configure the board using PMBus commands in
the evaluation software.
UG086 Rev.2.00
Nov 28, 2017
Page 2 of 23
ISL68201-99125DEMO1Z
Configuration
The default programming pins setting of the
ISL68201-99125DEMO1Z board can be found at the resistor
reader table on the lower left corner of
“ISL68201-99125DEMO1Z Schematics” on page 7
or read back
using the
PowerNavigator
software. Each PMBus command can
be loaded or programmed using PowerNavigator. Note that the
ISL68201 does not have NVM to store the operational
configuration; however, it can be set by the resistor programming
pins (PROG1-4) or programmed by the serial bus master before
powering up. If a serial bus master is available in the system, the
ISL68201-based rail can be fully controlled using software for
the power-up/power-down sequencing and operational
configuration without a soldering iron.
Load Transient
The on-board transient load can be controlled by a function
generator, whose inputs are connected to FG_DRIVE2 and
FG_GND2. The function generator’s output is terminated by R
42
at the input terminal, and its amplitude and dv/dt set the load
amplitude and di/dt on the 50mΩ load (R
LT1
/R
LT2
). The
transient load can be monitored with a scope probe on TP15.
Note that the duty cycle of applied load should be less than 10%
duty cycle with <10ms pulse width to keep the average power of
R
LT1/
R
LT2
less than its power rating.
OPEN JP4 FOR
EFFICIENCY MEASUREMENT
FIGURE 4. ON-BOARD LOAD TRANSIENT
FIGURE 5. ISL68201-99125DEMO1Z DEMONSTRATION KIT SETUP
UG086 Rev.2.00
Nov 28, 2017
Page 3 of 23
ISL68201-99125DEMO1Z
Design Modifications
Any modifications to the design will require new L/DCR matching
for a different inductor, a divider on the PROG pins for a different
operational configuration, R
SEN1
for OCP, an I
OUT
network for
accurate digital I
OUT
, a higher input capacitor rating to support
higher than 16V input, and a higher output capacitor rating to
support higher than 4V output. Refer to the
ISL68201
datasheet
and
PowerNavigator
software for proper design modifications
including L/DCR matching, thermal compensation, OCP, and
digital I
OUT
fine tuning.
Three examples are provided in
Table 1,
showing the
recommended design modifications to accommodate the
application cases with 5V and 3.3V output voltages. Some
fine-tuning might be needed depending upon the rework and
final layout design.
For the 5V input voltage applications with 4.5V < V
IN
< 5.5V
requirement, the “VIN”, “VCC”, “PVCC” and “7VLDO” pins should
be shorted together to connect with the input supply for optimal
performance. R
12
should be removed as well.
Note that all devices in the same bus should set different
addresses for unique identification and proper communication.
JP2, 3, 9 and 10 connectors are designed to cascade many
Intersil’s solutions for easy communication and system
evaluation before system integration and design.
TABLE 1. DESIGN EXAMPLES
REFERENCE
DESIGNATOR
L1
5.0V AT 16A
No change
3.3V AT 30A
470nH, 0.165mΩ
Vendor: Wurth Electronic;
Part Number: 744309047
No change
1.0V AT 20A
COMMENTS
Reduce output ripple current; higher voltage
220nH, 0.29mΩ
Vendor: Wurth Electronic; output typically needs higher inductance.
Part Number: 744307022
220µF/X5R/4V/1206
Vendor: Murata;
Part Number:
GRM31CR60G227ME11
Increase C
OUT
rating to support higher V
OUT
.
Also capacitance of ceramic capacitors
decreases with increased output voltage.
Set correct V
BOOT
= V
OUT
CO5, CO6, CO8,
CO9
PROG1 (DC)
R
3
PROG2 (DD)
R
5
R
6
PROG3 (DE)
R
8
R
9
PROG4 (DF)
R
10
R
11
CC1
R
P1
R
SEN1
R
13
R
14
DFh
147k, 1%
A0h
105k, 1%
DNP
0Dh
No change
No change
08h
No change
No change
No change
No change
No change
No change
TBD
BFh
No change
BFh
DNP
105k, 1%
0Dh
No change
No change
08h
No change
No change
1.0µF
3.57k, 1%
62, 1%
15k, 1%
TBD
80h
75k, 1%
BFh
DNP
105k, 1%
0Dh
19.6k, 1%
20k, 1%
00h
10k, 1%
DNP
No change
9.09k, 1%
75, 1%
9.53k, 1%
TBD
Set different PMBus addresses as needed
TCOMP = 15
PFM disabled
Set A
V
= 42 for 1.0V
f
SW
= 500kHz
OCP = Retry
25kHz clamp disabled
Set RR = 200k for 1.0V
SS = 1.25mV/µs
AVMLTI = 1x
L/DCR matching
Set OCP
Set I
OUT
to 1A/1A slope
Pull-up value depends upon final layout
design.
NOTE: Some fine-tuning might be needed depending upon the rework and final layout design.
UG086 Rev.2.00
Nov 28, 2017
Page 4 of 23
ISL68201-99125DEMO1Z
Design and Layout
Considerations
To ensure a first pass design, the schematics design must be
done correctly and the board must be carefully laid out.
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board or internal layers.
The ground-plane layer should be in between power layers and
the signal layers to provide shielding. Often, the layer below the
top and the layer above the bottom should be the ground layers.
DC/DC converters have two sets of components: the power
components and the small signal components. The power
components are the most critical because they switch large
amounts of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first. These include
MOSFETs, input and output capacitors, and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, GND, PHASE, and BOOT.
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. Input high frequency capacitors should be
placed close to the drain of the upper MOSFETs and the source of
the lower MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. High frequency
output decoupling capacitors (ceramic) should be placed as
close as possible to the decoupling target, making use of the
shortest connection paths to any internal planes. Place the
components in such a way that the area under the IC has fewer
noise traces with high dv/dt and di/dt, such as gate signals,
phase node signals, and VIN plane.
Tables 2
and
3
provide a design and layout checklist that a
designer should pay attention to.
TABLE 2. DESIGN AND LAYOUT CHECKLIST
PIN
NAME
EN
NOISE
SENSITIVITY
Yes
DESCRIPTION
There is an internal 1µs filter. Decoupling the
capacitor is NOT needed. However, if needed,
use a low time constant one to avoid too large
a shutdown delay.
Place a 16V+ X7R 1µF in close proximity to the
VIN pin and the system ground plane.
Place a 10V+ X7R 1µF in close proximity to the
7VLDO pin and the system ground plane.
Place a X7R 1µF in close proximity to the VCC
pin and the system ground plane.
TABLE 2. DESIGN AND LAYOUT CHECKLIST (Continued)
PIN
NAME
SCL, SDA
NOISE
SENSITIVITY
Yes
DESCRIPTION
50kHz to 1.25MHz signal when the SMBus,
PMBus, or I
2
C is sending commands. Pairing
up with SALERT and routing carefully back to
the SMBus, PMBus, or I
2
C master. 20 mils
spacing within SDA, SALERT, and SCL; and
more than 30 mils to all other signals. Refer to
the SMBus, PMBus, or I
2
C design guidelines
and place proper terminated (pull-up)
resistance for impedance matching. Tie them
to GND when not used.
Open-drain and high dv/dt pin during
transitions. Route it in the middle of SDA and
SCL. Tie it to GND when not used.
Open-drain pin. Tie it to ground when not used.
Differential pair routed to the remote sensing
points with sufficient decoupling ceramics
capacitors and not across or go above/under
any switching nodes (BOOT, PHASE, UGATE,
LGATE) or planes (VIN, PHASE, VOUT) even
though they are not in the same layer. At least
20 mils spacing from other traces. DO NOT
share the same trace with CSRTN.
Connect to the output rail side of the output
inductor or current sensing resistor pin with a
series resistor in close proximity to the pin. The
series resistor sets the current gain and should
be within 40Ω and 3.5kΩ. Decoupling
(~0.1µF/X7R) on the output end (not the pin) is
optional and might be required for long sense
traces or challenging layouts.
Connect to the phase node side of the output
inductor or current sensing resistor pin with
L/DCR or ESL/R
SEN
matching network in close
proximity to the CSEN and CSRTN pins.
Differentially routing back to the controller
with at least 20 mils spacing from other traces.
Should NOT cross or go above/under the
switching nodes [BOOT, PHASE, UGATE, LGATE]
and power planes (VIN, PHASE, VOUT) even
though they are not in the same layer.
Place NTC 10k (Murata, NCP15XH103J03RC,
= 3380) in close proximity to the output
inductor’s output rail, not close to MOSFET
side; the return trace should be 20 mils away
from other traces. Place 1.54kΩ pull-up and
decoupling capacitor (typically 0.1µF) in close
proximity to the controller. The pull-up resistor
should be exactly tied to the same point as the
VCC pin, not through an RC filter. If not used,
connect this pin to VCC.
Scale R so that the IOUT pin voltage is 2.5V at
63.875A load. Place R and C in general
proximity to the controller. The time constant
of RC should be sufficient as an averaging
function for the digital I
OUT
. An external pull-up
resistor to VCC is recommended to cancel I
OUT
offset at 0A load.
SALERT
No
PGOOD
RGND,
VSEN
No
Yes
CSRTN
Yes
CSEN
Yes
NTC
Yes
VIN
7VLDO
VCC
Yes
Yes
Yes
IOUT
Yes
UG086 Rev.2.00
Nov 28, 2017
Page 5 of 23
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