S25FL256L/S25FL128L
256-Mb (32-MB)/128-Mb (16-MB),
3.0 V FL-L Flash Memory
General Description
The Cypress FL-L Family devices are Flash non-volatile memory products using:
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Floating Gate technology
65 nm process lithography
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides
individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match
or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,
executing code directly (XIP), and storing re-programmable data.
Features
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Serial Peripheral Interface (SPI) with Multi-I/O
❐
Clock polarity and phase modes 0 and 3
❐
Double Data Rate (DDR) option
❐
Quad peripheral Interface (QPI) option
❐
Extended Addressing: 24- or 32-bit address options
❐
Serial Command subset and footprint compatible with
S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI
families
❐
Multi I/O Command subset and footprint compatible with
S25FL-P, S25FL-S and S25FS-S SPI families
Read
❐
Commands: Normal, Fast, Dual I/O, Quad I/O, DualO,
QuadO, DDR Quad I/O.
❐
Modes: Burst Wrap, Continuous (XIP), QPI
❐
Serial Flash Discoverable Parameters (SFDP) for configura-
tion information.
Program Architecture
❐
256 Bytes Page Programming buffer
❐
3.0 V FL-L Flash Memory
❐
Program suspend and resume
Erase Architecture
❐
Uniform 4 KB Sector Erase
❐
Uniform 32 KB Half Block Erase
❐
Uniform 64 KB Block Erase
❐
Chip erase
❐
Erase suspend and resume
100,000 Program/Erase Cycles, minimum
20 Year Data Retention, minimum
■
Security features
❐
Status and Configuration Register Protection
❐
Four Security Regions of 256 bytes each outside the main
Flash array
❐
Legacy Block Protection: Block range
❐
Individual and Region Protection
• Individual Block Lock: Volatile individual Sector/Block
• Pointer Region: Non-Volatile Sector/Block range
• Power Supply Lock-down, Password, or Permanent pro-
tection of Security Regions 2 and 3 and Pointer Region
Technology
❐
65 nm Floating Gate Technology
Single Supply Voltage with CMOS I/O
❐
2.7 V to 3.6 V
Temperature Range / Grade
❐
Industrial (–40 °C to +85 °C)
❐
Industrial Plus (–40 °C to +105 °C)
❐
Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
❐
Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
❐
Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)
Packages (all Pb-free)
❐
8-pin SOIC 208 mil (SOC008) — S25FL128L only
❐
WSON 5
6 mm (WND008) — S25FL128L only
❐
WSON 6
8 mm (WNG008) — S25FL256L only
❐
16-pin SOIC 300 mil (SO3016)
❐
BGA-24 6
8 mm
• 5
5 ball (FAB024) footprint
• 4
6 ball (FAC024) footprint
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Cypress Semiconductor Corporation
Document Number: 002-00124 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 11, 2018
S25FL256L/S25FL128L
Contents
1.
1.1
2.
2.1
2.2
2.3
2.4
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
4.
4.1
5.
5.1
5.2
5.3
5.4
6.
6.1
6.2
6.3
6.4
6.5
6.6
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.
8.1
8.2
8.3
8.4
8.5
Product Overview
........................................................ 4
Migration Notes.............................................................. 4
Connection Diagrams..................................................
SOIC 16-Lead ................................................................
8 Connector Packages...................................................
BGA Ball Footprint .........................................................
Special Handling Instructions for FBGA Packages........
5
5
5
6
6
8.6
8.7
8.8
8.9
8.10
8.11
8.12
9.
9.1
9.2
Erase Flash Array Commands...................................... 92
Security Regions Array Commands............................ 100
Individual Block Lock Commands ............................... 102
Pointer Region Command........................................... 107
Individual and Region Protection (IRP) Commands ... 108
Reset Commands ....................................................... 115
Deep Power Down Commands................................... 116
Data Integrity
............................................................. 119
Erase Endurance ........................................................ 119
Data Retention ............................................................ 119
Signal Descriptions
..................................................... 7
Input/Output Summary................................................... 7
Multiple Input / Output (MIO).......................................... 8
Serial Clock (SCK) ......................................................... 8
Chip Select (CS#) .......................................................... 8
Serial Input (SI) / IO0 ..................................................... 8
Serial Output (SO) / IO1................................................. 8
Write Protect (WP#) / IO2 .............................................. 8
IO3 / RESET# ................................................................ 9
RESET# ......................................................................... 9
Voltage Supply (V
CC
)..................................................... 9
Supply and Signal Ground (V
SS
) ................................... 9
Not Connected (NC) ...................................................... 9
Reserved for Future Use (RFU)................................... 10
Do Not Use (DNU) ....................................................... 10
Block Diagram............................................................
11
System Block Diagrams............................................... 11
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Data Protection ............................................................
13
13
14
18
22
10. Software Interface Reference
.................................. 120
10.1 JEDEC JESD216B Serial Flash Discoverable
Parameters ................................................................. 120
10.2 Device ID Address Map .............................................. 129
10.3 Initial Delivery State .................................................... 129
11.
11.1
11.2
11.3
11.4
11.5
11.6
12.
12.1
12.2
12.3
12.4
12.5
12.6
Electrical Specifications...........................................
130
Absolute Maximum Ratings ........................................ 130
Latchup Characteristics .............................................. 130
Thermal Resistance .................................................... 130
Operating Ranges....................................................... 131
Power-Up and Power-Down ....................................... 132
DC Characteristics ...................................................... 134
Timing Specifications...............................................
137
Key to Switching Waveforms ...................................... 137
AC Test Conditions ..................................................... 137
Reset .......................................................................... 138
SDR AC Characteristics ............................................. 141
DDR AC Characteristics ............................................. 144
Embedded Algorithm Performance Tables ................. 146
Address Space Maps.................................................
23
Overview ...................................................................... 23
Flash Memory Array..................................................... 23
ID Address Space ........................................................ 24
JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space.............................................................. 24
Security Regions Address Space ................................ 24
Registers...................................................................... 25
Data Protection
..........................................................
Security Regions..........................................................
Deep Power Down .......................................................
Write Enable Commands .............................................
Write Protect Signal .....................................................
Status Register Protect (SRP1, SRP0)........................
Array Protection ...........................................................
Individual and Region Protection .................................
Commands
.................................................................
Command Set Summary..............................................
Identification Commands .............................................
Register Access Commands........................................
Read Memory Array Commands .................................
Program Flash Array Commands ................................
43
43
43
44
44
45
46
53
58
58
64
68
82
90
13. Ordering Information
................................................ 147
13.1 Ordering Part Number................................................. 147
14.
14.1
14.2
14.3
14.4
14.5
14.6
15.
15.1
15.2
15.3
15.4
Physical Diagrams
.................................................... 150
SOIC 16-Lead, 300-mil Body Width (SO3016) ........... 150
SOIC 8-Lead, 208 mil Body Width (SOC008)............. 151
WSON 8-Contact 5 x 6 mm Leadless (WND008) ....... 152
WSON 8-Contact 6 x 8 mm Leadless (WNG008)....... 153
Ball Grid Array 24-ball 6 x 8 mm (FAB024)................. 154
Ball Grid Array 24-ball 6 x 8 mm (FAC024) ................ 155
Other Resources
....................................................... 156
Glossary...................................................................... 156
Link to Cypress Flash Roadmap................................. 157
Link to Software .......................................................... 157
Link to Application Notes ............................................ 157
16. Document History
..................................................... 158
Sales, Solutions, and Legal Information ......................... 160
Worldwide Sales and Design Support .......................... 160
Products ....................................................................... 160
PSoC® Solutions ......................................................... 160
Cypress Developer Community .................................... 160
Technical Support ........................................................ 160
Document Number: 002-00124 Rev. *H
Page 3 of 160
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