AT25QL641
64-Mbit, 1.7V Minimum
SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support
Features
Single 1.7V - 2.0V Supply
Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read and Quad I/O program and read
Supports QPI program and read
133 MHz maximum operating frequency
Clock-to-Output (t
V1
) of 6 ns
Up tp 66 MB/s continuous data transfer rate
Quad enabled (factory default setting: see
Section 6.7)
Full chip erase
Flexible, optimized erase architecture for code and data storage applications
0.6 ms typical Page Program (256 Bytes) time
60 ms typical 4 Kbyte Block Erase time
200 ms typical 32 Kbyte Block Erase time
350 ms typical 64 Kbyte Block Erase time
Hardware controlled locking of Status registers via WP pin
4 Kbit secured One-Time Programmable (OTP) security register
Hardware write protection
Serial Flash Discoverable Parameters (SFDP) register
Flexible programming
Byte/page program (1 to 256 Bytes)
Dual or quad input byte/page program (1 to 256 Bytes)
Erase/program suspend and resume
JEDEC standard manufacturer and device ID read methodology
Low power dissipation
2 µA Deep Power-Down (DPD) current (typical)
10 µA Standby current (typical)
5 mA Active read current (typical)
Endurance: 100,000 program/erase cycles (4KB, 32KB or 64KB blocks)
Data Retention: 20 years
Industrial temperature range: -40 °C to +85 °C
Industry standard green (Pb/Halide-free/RoHS compliant) package options
8-lead SOIC (0.208” Wide EIAJ)
8-pad DFN (6 x 5 x 0.6 mm)
8-ball WLCSP (dBGA)
DS-25QL641–130E–10/2018
1.
Introduction
The Adesto
®
AT25QL641 is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25QL641 is ideal for data storage as well, eliminating the need for
additional data storage devices.
The erase block sizes of the AT25QL641 have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
SPI clock frequencies of up to 133 MHz are supported, allowing equivalent clock rates of 266 MHz for Dual Output and
532 MHz for Quad Output when using the QPI and Fast Read Dual/Quad I/O instructions.The AT25QL641 array is
organized into
32,768
programmable pages of 256 bytes each. Up to 256 bytes can be programmed at a time using the
Page Program instructions. Pages can be erased 4 KB block, 32 KB block, 64 KB block, or the entire chip.
The devices operate on a single 1.7V to 1.95V power supply with current consumption as low as 5 mA active and 2
µ
A for
Deep Power Down (DPD). All devices offered in space-saving packages. The device supports JEDEC standard
manufacturer and device identification with a 4 Kbit secured OTP.
AT25QL641
DS-25QL641–130E–10/2018
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2.
Pinouts and Pin Descriptions
The following figures show the available package types.
Figure 1-1. 8-SOIC (Top View)
Figure 1-2. 8-UDFN (Top View)
CS
SO (IO
1
)
WP (IO
2
, ACC)
GND
1
2
3
4
8
7
6
5
VCC
HOLD (IO
3
)
SCK
SI (IO
0
)
CS
SO (IO
1
)
WP (IO
2
, ACC)
GND
1
2
3
4
8
7
6
5
VCC
HOLD (IO
3
)
SCK
SI (IO
0
)
Figure 1-3. 8-WLCSP (Bottom View)
NC
NC
CS
Vcc
I/O
1
(SO)
I/O
3
(HOLD)
I/O
2
(WP)
SCK
GND
I/O
0
(SI)
NC
NC
During all operations,
V
CC
must be held stable and within the specified valid range:
V
CC
(min) to
V
CC
(max).
All of the input and output signals must be held high or low (according to voltages of V
IH
, V
OH
, V
IL
or V
OL
).
AT25QL641
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Table 1-1.
Pin Descriptions
Asserted
State
Symbol
Name and Function
CHIP SELECT
Type
CS
When this input signal is high, the device is deselected and serial data output pins are at
high impedance. Unless an internal program, erase or write status register cycle is in
progress, the device remains in the standby power mode (this is not the deep power
down mode). Driving the Chip Select (CS) low enables the device, placing it in the active
power mode. After power-up, a falling edge of Chip Select (CS) is required prior to the
start of any instruction.
SERIAL CLOCK
Low
Input
SCK
This input signal provides the timing for the serial interface. Instructions, addresses, or data
present at serial data input are latched on the rising edge of Serial Clock (SCK). Data are
shifted out on the falling edge of the SCK.
SERIAL INPUT
The SI pin is used to shift data into the device. The SI pin is used for all data input, including
command and address sequences. Data on the SI pin is always latched in on the rising edge
of SCK.
-
Input
SI (I/O
0
)
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin
(I/O
0
) in conjunction with other pins to allow two or four bits of data on (I/O
3-0
) to be clocked in
on every falling edge of SCK
To maintain consistency with the SPI nomenclature, the SI (I/O
0
) pin is referenced as the SI
pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it is
referenced as I/O
0.
Data present on the SI pin is ignored whenever the device is deselected (CS is deasserted).
SERIAL OUTPUT
The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out
on the falling edge of SCK.
-
Input/Output
SO (I/O
1
)
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O
0
) in conjunction
with other pins to allow two bits of data on (I/O
1-0
) to be clocked in on every falling edge of
SCK.
To maintain consistency with the SPI nomenclature, the SO (I/O
1
) pin is referenced as the SO
pin unless specifically addressing the Dual-I/O modes in which case it is referenced as I/O
1.
The SO pin is in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT
-
Input/Output
WP (I/O
2
)
The Write Protect (WP) pin can be used to protect the Status register against data
modification. Used in conjunction with the Block Protect (SEC, TB, BP2, BP1 and BP0) bits
and Status Register Protect SRP) bits, a portion or the entire memory array can be hardware-
protected. The WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,
the WP pin (Hardware Write Protect) function is not available since this pin is used for I/O
2
.
-
Input/Output
AT25QL641
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Table 1-1.
Pin Descriptions (Continued)
Asserted
State
Symbol
Name and Function
HOLD
The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on
the SI pin are ignored and the SO pin is placed in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle.
Type
HOLD
(I/O
3
)
With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin (I/O
3
)
and with other pins, allows four bits (on I/O
3-0
) of data to be clocked in on every rising edge of
SCK. With the Quad-Output Read commands, the HOLD Pin becomes an output pin (I/O
3
) in
conjunction with other pins to allow four bits of data on (I/O3
3-0
) to be clocked in on every
falling edge of SCK.
To maintain consistency with SPI nomenclature, the HOLD (I/O
3
) pin is referenced as the
HOLD pin unless specifically addressing the Quad-I/O modes in which case it is referenced as
I/O
3.
The HOLD pin is internally pulled-high and may be left floating if the Hold function is not
used. However, it is recommended that the HOLD pin also be externally connected to V
CC
whenever possible.
DEVICE POWER SUPPLY:
V
CC
is the supply voltage. It is the single voltage used for all
device functions including read, program, and erase.
The V
CC
pin is used to supply the
source voltage to the device. Operations at invalid V
CC
voltages may produce spurious results
and should not be attempted.
GROUND:
V
SS
is the reference for the
V
CC
supply voltage.
The ground reference for the
power supply. GND should be connected to the system ground.
-
Input/Output
V
CC
-
Power
GND
-
Power
AT25QL641
DS-25QL641–130E–10/2018
5
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