AT25QL641-UUE-T datasheet, PDF

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AT25QL641-UUE-T: DescriptionNOR Flash QPI,8- WLCSP, IND TEMP, 1.8V, T&R; Categorysemiconductor Memory IC NOR flash memory; File Size6MB，77 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT25QL641-UUE-T Overview

NOR Flash QPI,8- WLCSP, IND TEMP, 1.8V, T&R

AT25QL641-UUE-T Parametric

Parameter Name	Attribute value
Maker	Adesto Technologies
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	WLCSP-8
series	AT25QL641
storage	64 Mbit
maximum clock frequency	104 MHz
Interface Type	QPI, SPI
Timing type	Synchronous
Supply voltage - min.	1.7 V
Supply voltage - max.	2 V
Supply current—max.	20 mA
Minimum operating temperature	- 40 C
Encapsulation	Reel
storage type	Flash
speed	104 MHz
Factory packaging quantity	5000

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AT25QL641

64-Mbit, 1.7V Minimum

SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

Features

Single 1.7V - 2.0V Supply

Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) compatible

Supports SPI Modes 0 and 3

Supports Dual Output Read and Quad I/O program and read

Supports QPI program and read

133 MHz maximum operating frequency

Clock-to-Output (t

) of 6 ns

Up tp 66 MB/s continuous data transfer rate

Quad enabled (factory default setting: see

Section 6.7)

Full chip erase

Flexible, optimized erase architecture for code and data storage applications

0.6 ms typical Page Program (256 Bytes) time

60 ms typical 4 Kbyte Block Erase time

200 ms typical 32 Kbyte Block Erase time

350 ms typical 64 Kbyte Block Erase time

Hardware controlled locking of Status registers via WP pin

4 Kbit secured One-Time Programmable (OTP) security register

Hardware write protection

Serial Flash Discoverable Parameters (SFDP) register

Flexible programming

Byte/page program (1 to 256 Bytes)

Dual or quad input byte/page program (1 to 256 Bytes)

Erase/program suspend and resume

JEDEC standard manufacturer and device ID read methodology

Low power dissipation

2 µA Deep Power-Down (DPD) current (typical)

10 µA Standby current (typical)

5 mA Active read current (typical)

Endurance: 100,000 program/erase cycles (4KB, 32KB or 64KB blocks)

Data Retention: 20 years

Industrial temperature range: -40 °C to +85 °C

Industry standard green (Pb/Halide-free/RoHS compliant) package options

8-lead SOIC (0.208” Wide EIAJ)

8-pad DFN (6 x 5 x 0.6 mm)

8-ball WLCSP (dBGA)

DS-25QL641–130E–10/2018

Table 1-1.

Pin Descriptions

Asserted

State

Symbol

Name and Function

CHIP SELECT

Type

When this input signal is high, the device is deselected and serial data output pins are at

high impedance. Unless an internal program, erase or write status register cycle is in

progress, the device remains in the standby power mode (this is not the deep power

down mode). Driving the Chip Select (CS) low enables the device, placing it in the active

power mode. After power-up, a falling edge of Chip Select (CS) is required prior to the

start of any instruction.

SERIAL CLOCK

Low

Input

SCK

This input signal provides the timing for the serial interface. Instructions, addresses, or data

present at serial data input are latched on the rising edge of Serial Clock (SCK). Data are

shifted out on the falling edge of the SCK.

SERIAL INPUT

The SI pin is used to shift data into the device. The SI pin is used for all data input, including

command and address sequences. Data on the SI pin is always latched in on the rising edge

of SCK.

Input

SI (I/O

)

With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin

(I/O

) in conjunction with other pins to allow two or four bits of data on (I/O

3-0

) to be clocked in

on every falling edge of SCK

To maintain consistency with the SPI nomenclature, the SI (I/O

) pin is referenced as the SI

pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it is

referenced as I/O

Data present on the SI pin is ignored whenever the device is deselected (CS is deasserted).

SERIAL OUTPUT

The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out

on the falling edge of SCK.

Input/Output

SO (I/O

)

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O

) in conjunction

with other pins to allow two bits of data on (I/O

1-0

) to be clocked in on every falling edge of

SCK.

To maintain consistency with the SPI nomenclature, the SO (I/O

) pin is referenced as the SO

pin unless specifically addressing the Dual-I/O modes in which case it is referenced as I/O

The SO pin is in a high-impedance state whenever the device is deselected (CS is

deasserted).

WRITE PROTECT

Input/Output

WP (I/O

)

The Write Protect (WP) pin can be used to protect the Status register against data

modification. Used in conjunction with the Block Protect (SEC, TB, BP2, BP1 and BP0) bits

and Status Register Protect SRP) bits, a portion or the entire memory array can be hardware-

protected. The WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,

the WP pin (Hardware Write Protect) function is not available since this pin is used for I/O

Input/Output

AT25QL641

DS-25QL641–130E–10/2018

AT25QL641-UUE-T Related Products

	AT25QL641-UUE-T	AT25QL641-SUE-T	AT25QL641-UCUE-T
Description	NOR Flash QPI,8- WLCSP, IND TEMP, 1.8V, T&R	NOR Flash Die in Wafer Form	NOR flash QPI,18-WLCSP, IND TEMP, 1.8V, T&R
Maker	Adesto Technologies	Adesto Technologies	Adesto Technologies
Product Category	NOR flash memory	NOR flash memory	NOR flash memory
Installation style	SMD/SMT	SMD/SMT	SMD/SMT
Package/box	WLCSP-8	SOIC-8	WLCSP-18
series	AT25QL641	AT25QL641	AT25QL641
storage	64 Mbit	64 Mbit	64 Mbit
maximum clock frequency	104 MHz	104 MHz	104 MHz
Interface Type	QPI, SPI	QPI, SPI	QPI, SPI
Timing type	Synchronous	Synchronous	Synchronous
Supply voltage - min.	1.7 V	1.7 V	1.7 V
Supply voltage - max.	2 V	2 V	2 V
Supply current—max.	20 mA	20 mA	20 mA
Minimum operating temperature	- 40 C	- 40 C	- 40 C
storage type	Flash	Flash	Flash
speed	104 MHz	104 MHz	104 MHz
Factory packaging quantity	5000	2000	5000
Encapsulation	Reel	Reel	Reel

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