SAMA5D2 Series
Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU,
500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB,
PCI 5.0 Pre-Certified
Introduction
The SAMA5D2 series is a high-performance, ultra-low-power Arm Cortex-A5 CPU-based embedded
microprocessor (MPU) running up to 500 MHz, with support for multiple memories such as DDR2,
DDR3L, LPDDR2, LPDDR3, and QSPI and e.MMC Flash. The devices integrate powerful peripherals for
®
connectivity and user interface applications, and offer advanced security functions (Arm TrustZone ,
tamper detection, secure data storage, etc.), as well as high-performance crypto accelerators AES, SHA
and TRNG.
Selected members of the SAMA5D2 series are qualified for extended industrial temperature range
operation (-40°C to 105°C external temperature).
The SAMA5D2 series is delivered with a free Linux distribution and bare metal C examples.
®
Features
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Arm Cortex-A5 Core
– Armv7-A architecture
– Arm TrustZone
™
– NEON Media Processing Engine
– Up to 500 MHz
– ETM/ETB 8 Kbytes
Memory Architecture
– Memory Management Unit (MMU)
– 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
– 128-Kbyte L2 cache configurable to be used as an internal SRAM
– One 128-Kbyte scrambled internal SRAM
One 160-Kbyte internal ROM
• 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader
• 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
– High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM
controller supporting up to 512 Mbytes 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off
only) / LPDDR1/LPDDR2/LPDDR3, including “on-the-fly” encryption/decryption path
– 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
System Running up to 166 MHz in Typical Conditions
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2018 Microchip Technology Inc.
Datasheet Complete
DS60001476C-page 1
SAMA5D2 Series
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Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer (PIT),
independent Watchdog Timer (WDT) and secure Real-Time Clock (RTC) with clock calibration
One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for high-speed USB
Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)
Internal low-power 12 MHz RC and 32 kHz typical RC
Selectable 32.768 Hz low-power oscillator and 8 to 24 MHz oscillator
51 DMA channels including two 16-channel 64-bit Central DMA Controllers
64-bit Advanced Interrupt Controller (AIC)
64-bit Secure Advanced Interrupt Controller (SAIC)
– Three programmable external clock signals
Low-Power Modes
– Ultra-low-power mode with fast wake-up capability
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Low-power Backup mode with 5-Kbyte SRAM and SleepWalking
™
features
• Wake up from up to nine wake-up pins, UART reception, analog comparison
• Fast wake-up capability
• Extended Backup mode with DDR in Self-Refresh mode
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Peripherals
– LCD TFT controller (LCDC) up to 1024x768 or 1280x768 (still image). Four overlays, rotation,
post-processing and alpha blending, 24-bit parallel RGB interface
– ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 Mpixel sensors with a
parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor
interface
– Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one
Stereo Class D amplifier (CLASSD)
– One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive
touch)
– One Pulse Density Modulation Interface Controller (PDMIC)
– One USB device high-speed port (UDPHS) and one USB host high-speed port or two USB host
high-speed ports (UHPHS)
– One USB host high-speed port with a High-Speed Inter-Chip (HSIC) interface
– One 10/100 Ethernet MAC (GMAC)
• Energy efficiency support (IEEE
®
802.3az standard)
• Ethernet AVB support with IEEE802.1AS timestamping
• IEEE802.1Qav credit-based traffic-shaping hardware support
• IEEE1588 Precision Time Protocol (PTP)
– Two high-speed memory card hosts:
• SDMMC0: SD 3.0, eMMC 4.51, 8 bits
• SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
– Two master/slave Serial Peripheral Interfaces (SPI)
– Two Quad Serial Peripheral Interfaces (QSPI)
– Five FLEXCOMs (USART, SPI and TWI)
– Five UARTs
– Two master CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-
triggered transmission
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2018 Microchip Technology Inc.
Datasheet Complete
DS60001476C-page 2
SAMA5D2 Series
WARNING
MCAN implements the non-ISO CAN FD frame format and therefore does not pass the
CAN FD Conformance Test according to ISO 16845-1:2016.
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– One Rx only UART in backup area (RXLP)
– One Analog Comparator Controller (ACC) in backup area
– Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I
2
C protocol and SMBUS
– One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller
– Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes
– One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with resistive touchscreen capability
Safety
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Zero-power Power-on Reset (POR) cells
Main crystal clock failure detector
Write-protected registers
Integrity Check Monitor (ICM) based on SHA256
Memory Management Unit (MMU)
Independent watchdog
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Security
– 5 Kbytes of internal scrambled SRAM:
• 1 Kbyte nonerasable on tamper detection
• 4 Kbytes erasable on tamper detection
– 256 bits of scrambled and erasable registers
– Up to eight tamper pins for static or dynamic intrusion detections
(1)
– Environmental monitors on specific versions: temperature, voltage, frequency and active die
shield
(2)
– Secure Bootloader
(3)
– On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB)
– RTC including timestamping on security intrusions
– Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)
Note:
1. For information specific to dynamic tamper protection (PIOBU), refer to the document
SAMA5D2External Tamper Protections
(document no. 44095).
2. For environmental monitors, refer to the document
SAMA5D23 and SAMA5D28
Environmental Monitors
(document no. 44036), available under Non-Disclosure Agreement
(NDA). Contact a Microchip Sales Representative for details.
3. For secure boot strategies, refer to the document
SAMA5D2 Series Secure Boot Strategy
(document no. 44040), available under Non-Disclosure Agreement (NDA). Contact a
Microchip Sales Representative for details.
Hardware Cryptography
– SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2
– AES: 256-, 192-, 128-bit key algorithms, compliant with FIPS PUB 197
– TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
– True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test
Suite and FIPS PUBs 140-2 and 140-3
Up to 128 I/Os
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2018 Microchip Technology Inc.
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SAMA5D2 Series
Fully programmable through set/clear registers
Multiplexing of up to eight peripheral functions per I/O line
Each I/O line can be assigned to a peripheral or used as a general-purpose I/O
The PIO controller features a synchronous output providing up to 32 bits of data output in one
write operation
Packages
– 289-ball LFBGA, 14 x 14 mm body, 0.8 mm pitch
– 256-ball TFBGA, 8 x 8 mm body, 0.4 mm pitch
– 196-ball TFBGA, 11 x 11 mm body, 0.75 mm pitch
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2018 Microchip Technology Inc.
Datasheet Complete
DS60001476C-page 4
SAMA5D2 Series
Description
1.
Description
The SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the Arm Cortex-
A5 processor. It integrates the Arm NEON SIMD engine for accelerated multimedia and signal
processing, a configurable 128-Kbyte L2 cache and a floating point unit (FPU) for high-precision
computing. The device features an advanced user interface and connectivity peripherals. Advanced
security is provided by powerful cryptographic accelerators, by the Arm TrustZone technology securing
access to memories and sensitive peripherals, and by several hardware features that safeguard memory
content, authenticate software, detect physical attacks and prevent information leakage during code
execution.
The SAMA5D2 features an internal multilayer bus architecture associated with 2 x 16 DMA channels and
dedicated DMAs for the communication and interface peripherals required to ensure uninterrupted data
transfers with minimal processor overhead. The device supports DDR2, DDR3, DDR3L, LPDDR1,
LPDDR2, LPDDR3, QSPI and e.MMC Flash, and SLC/MLC parallel NAND Flash memory up to 32-bit
ECC.
The comprehensive peripheral set includes an LCD TFT controller with overlays for hardware-accelerated
image composition, an image sensor controller, audio support through I
2
S, SSC, a stereo Class D
amplifier and a digital microphone. Connectivity peripherals include a 10/100 EMAC, USBs, CANs,
FLEXCOMs, UARTs, SPIs and two QSPIs, SDIO/SD/e.MMCs, and TWIs/I
2
C.
Protection of code and data is provided by automatic scrambling of memories and an Integrity Check
Monitor (ICM) to detect any modification of the memory contents. The SAMA5D2 also supports execution
of encrypted code (QSPI or one portion of the DDR) with an “on-the-fly” encryption-decryption process.
With its secure design architecture, cryptographic acceleration engines, and secure bootloader, the
SAMA5D2 is the ideal solution for point-of-sale (POS), IoT and industrial applications requiring device
authentication, anti-cloning, data protection and secure communication.
SAMA5D2 devices feature three software-selectable low-power modes: Idle, Ultra-Low-Power and
Backup.
In Idle mode, the processor is stopped while all other functions can be kept running.
In Ultra-Low-Power mode 0, the processor is stopped while all other functions are clocked at 512 Hz and
interrupts or peripherals can be configured to wake up the system based on events, including partial
asynchronous wake-up (SleepWalking).
In Ultra-Low-Power mode 1, all clocks and functions are stopped but some peripherals can be configured
to wake up the system based on events, including partial asynchronous wake-up (SleepWalking).
In Backup mode, RTC and wake-up logic are active. The Backup mode can be extended to feature DDR
in Self-refresh mode.
SAMA5D2 devices also include an Event System that allows peripherals to receive, react to and send
events in Active and Idle modes without processor intervention.
©
2018 Microchip Technology Inc.
Datasheet Complete
DS60001476C-page 5
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