Quick Start
DEMO876xAH Demonstration Board for
ADC1206S040/055/070 family
Rev. 2.0 — 2 July 2012
Quick Start
Document information
Info
Keywords
Content
DEMO876xAH, PCB834-4, Demonstration board, ADC, Converter,
ADC1206S040/055/070
This document describes how to use the demonstration board
DEMO876xAH for the analog-to-digital converter ADC1206S040/055/070
family.
Abstract
Overview
Revision history
Rev
2.0
0.5
Date
20120702
20080610
Description
Rebranded.
Example added.
1. Quick start
1.1 Setup overview
Figure Fig 1
presents the connections to measure DEMO876xAH.
P
OWER SUPPLY
. 12V
. I = 135 mA
.GND
F
ILTER
. High-order
. Band pass
SYNTHESIZED
SIGNAL
GENERATOR
I
NPUT SIGNAL
. 2V
pp
sinewave
. AC
S
YNCHRONIZED
PULSE
GENERATOR
C
LOCK SIGNAL
(CLK)
For data
acquisition
PULSE
GENERATOR
C
LOCK SIGNAL
(CLK)
. TTL/CMOS
P
RESENTED CONFIGURATION
. 2V
pp
input full scale
. Input common mode from IC
. Input sample & hold ON
. Enabled ADC output
. Binary ADC output
Fig 1. DEMO876xAH setup
(MSB)
. D11
. D10
. D9
. D8
. D7
. D6
. D5
. D4
. D3
. D2
. D1
. D0
(LSB)
CLK for
data acqu.
LOGIC
ANALYZER
Output data
1.2 Power supply
The board is powered with a single 12 V
DC
power supply. A power supply regulator is
used to supply all the circuitry on the board.
Table 1.
Name
J4
D8
TM1
TM2
TM3
TP2
General power supply
Function
Green connector – Power supply 12 V
DC
/ 135 mA.
PWR green light – It indicates the good supply plugging
DGND test point – Digital ground
AGND test point – Analog ground
VCC test point – ADC core power supply
VCCO test point – Output stage power supply
View
1.3 Input signals (IN, CLK1)
To ensure a good evaluation of the device, the input signal and the input clock must be
synchronized together.
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
follow the formula:
,where M is an odd number of period and N is the number of samples.
Table 2.
Name
J1
J3
S5
Input signals
Function
IN connector – Analog input signal (
50
matching)
CLK1 connector – Clock input signal (
50
matching)
SH switch – Activation of the input sample-and-hold
View
Active
7MHz < Fclk < 70MHz
Tracking mode
Fi < 1 MHz
1.4 Output signals (D0 to D11, IR)
The digital output signal is available in binary or 2’s complement format.
An optional clock connector is available to simplify the acquisition clock generation.
Table 3.
Name
B8
B5
Output signals
Function
Array connector – ADC digital output (D0 to D11)
IR test point – It indicates the out of range state of the
analog input signal
View
J2-B11 CLK2 connector – Optional clock for the data acquisition
S3
OTC switch – Output format selection
Binary
S4
2’s complement
CEN switch – Output enable selection
Active output
High impedance output
1.5 Input common mode (CMADC)
The input common mode can be set by the internal reference of the ADC or can be
adjusted manually with a potentiometer.
Table 4.
Name
S1
Input common mode voltage adjustment
Function
Switch – Selection between internal and external
common mode
View
Internal common
mode
External common
mode
P1
B4
Potentiometer – External common mode adjustment
CMADC test point – input common mode
1.6 Input full scale (VREF)
The input full scale mode can be set by the internal reference of the ADC or can be
adjusted manually with a potentiometer.
Table 5.
Name
S2
Input full scale adjustment
Function
Ext switch – Selection between internal and external
reference voltage
View
Internal reference
P2
External reference
VREF potentiometer – External reference voltage
adjustment
VREF test point – VREF reference voltage
B7
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