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74AHC125BQ,115

Description
BUFFERS AND LINE DRIVERS 5V QUAD BUFF/LD ACTIVE LOW OUT
Categorylogic    logic   
File Size589KB,16 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Download Datasheet Parametric View All

74AHC125BQ,115 Overview

BUFFERS AND LINE DRIVERS 5V QUAD BUFF/LD ACTIVE LOW OUT

74AHC125BQ,115 Parametric

Parameter NameAttribute value
Brand NameNexperia
MakerNexperia
Parts packaging codeQFN
package instructionHVQCCN,
Contacts14
Manufacturer packaging codeSOT762-1
Reach Compliance Codecompliant
Samacsys Description74AHC(T)125 - Quad buffer/line driver; 3-state@en-us
seriesHC/UH
JESD-30 codeR-PQCC-N14
JESD-609 codee4
length3 mm
Logic integrated circuit typeBUS DRIVER
Humidity sensitivity level1
Number of digits1
Number of functions4
Number of ports2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Package shapeRECTANGULAR
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)14.5 ns
Certification statusNot Qualified
Maximum seat height1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width2.5 mm
Base Number Matches1
74AHC125; 74AHCT125
Quad buffer/line driver; 3-state
Rev. 04 — 11 January 2008
Product data sheet
1. General description
The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH
at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active
LOW enable inputs.
2. Features
s
s
s
s
s
s
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
CC
For 74AHC125 only: operates with CMOS input levels
For 74AHCT125 only: operates with TTL input levels
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101C exceeds 1000 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC125D
74AHCT125D
74AHC125PW
74AHCT125PW
74AHC125BQ
74AHCT125BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
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