S25FL127S
128-Mbit (16 Mbyte)
3.0 V SPI Flash Memory
Features
CMOS 3.0 Volt Core
Density
– 128 Mbits (16 Mbytes)
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Extended Addressing: 24- or 32-bit address options
– Serial Command set and footprint compatible with
S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad
– AutoBoot - power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information.
Programming (0.8 Mbytes/s)
– 256- or 512-byte Page Programming buffer options
– Quad-Input Page Programming (QPP) for slow clock
systems
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 Mbytes/s)
– Hybrid sector size option - physical set of sixteen 4-kbyte
sectors at top or bottom of address space with all
remaining sectors of 64 kbytes
– Uniform sector option - always erase 256-kbyte blocks for
software compatibility with higher density and future
devices.
Cycling Endurance
– 100,000 Program-Erase Cycles per sector, minimum
Data Retention
– 20 Year Data Retention, minimum
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against
program or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress 65 nm MirrorBit Technology with Eclipse
Architecture
Supply Voltage: 2.7V to 3.6V
Temperature Range:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
– Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
– Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
Packages (all Pb-free)
– 8-lead SOIC (208 mil)
– 16-lead SOIC (300 mil)
– 8-contact WSON 6 x 5 mm
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint
options
– Known Good Die and Known Tested Die
Cypress Semiconductor Corporation
Document Number: 001-98282 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 08, 2017
S25FL127S
Contents
Performance Summary
........................................................ 3
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
5.3
5.4
6.
6.1
6.2
6.3
6.4
6.5
7.
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
5
7
8
7.1
7.2
7.3
7.4
7.5
7.6
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Overview....................................................................... 47
Flash Memory Array...................................................... 47
ID-CFI Address Space .................................................. 48
JEDEC JESD216B Serial Flash Discoverable Parameters
(SFDP) Space............................................................... 48
OTP Address Space ..................................................... 49
Registers....................................................................... 50
Data Protection
........................................................... 59
Secure Silicon Region (OTP)........................................ 59
Write Enable Command................................................ 59
Block Protection ............................................................ 60
Advanced Sector Protection ......................................... 61
Commands
.................................................................. 66
Command Set Summary............................................... 67
Identification Commands .............................................. 72
Register Access Commands......................................... 75
Read Memory Array Commands .................................. 85
Program Flash Array Commands ................................. 93
Erase Flash Array Commands...................................... 97
One Time Program Array Commands ........................ 102
Advanced Sector Protection Commands .................... 103
Reset Commands ....................................................... 109
Embedded Algorithm Performance Tables ................. 110
Signal Descriptions
..................................................... 9
Input/Output Summary................................................... 9
Address and Data Configuration.................................. 10
Hardware Reset (RESET#).......................................... 10
Serial Clock (SCK) ....................................................... 10
Chip Select (CS#) ........................................................ 10
Serial Input (SI) / IO0 ................................................... 11
Serial Output (SO) / IO1............................................... 11
Write Protect (WP#) / IO2 ............................................ 11
Hold (HOLD#) / IO3 / RESET# .................................... 11
Voltage Supply (V
CC
)................................................... 12
Supply and Signal Ground (V
SS
) ................................. 12
Not Connected (NC) .................................................... 12
Reserved for Future Use (RFU)................................... 12
Do Not Use (DNU) ....................................................... 13
Block Diagrams............................................................ 13
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications
................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
AC Characteristics .......................................................
Physical Interface
......................................................
SOIC 8-Lead Package .................................................
SOIC 16-Lead Package ...............................................
WSON 6 x 5 Package ..................................................
FAB024 24-Ball BGA Package ....................................
FAC024 24-Ball BGA Package ....................................
15
15
15
19
24
24
25
25
25
26
28
29
29
30
31
34
37
37
39
41
43
45
10. Data Integrity
............................................................. 112
10.1 Erase Endurance ........................................................ 112
10.2 Data Retention ............................................................ 112
11. Software Interface Reference
.................................. 113
11.1 Command Summary ................................................... 113
12.
12.1
12.2
12.3
12.4
12.5
13.
Serial Flash Discoverable Parameters (SFDP)
Address Map
............................................................. 115
SFDP Header Field Definitions ................................... 116
Device ID and Common Flash Interface (ID-CFI)
Address Map............................................................... 118
Device ID and Common Flash Interface (ID-CFI) ASO Map
— Automotive Only ..................................................... 133
Registers..................................................................... 134
Initial Delivery State .................................................... 137
Ordering Information
................................................ 138
Address Space Maps
................................................. 47
14. Revision History........................................................
140
Sales, Solutions, and Legal Information .................... 142
Worldwide Sales and Design Support .......................... 142
Products ....................................................................... 142
PSoC® Solutions ......................................................... 142
Cypress Developer Community .................................... 142
Technical Support ........................................................ 142
Document Number: 001-98282 Rev. *I
Page 3 of 142
S25FL127S
1. Overview
1.1
General Description
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
The Cypress S25FL127S device is a flash non-volatile memory product using:
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single
I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple
width interface is called SPI Multi-I/O or MIO.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to
be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO command, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous,
NOR flash memories while reducing signal count dramatically.
The S25FL127S product offers a high density coupled with the flexibility and fast performance required by a variety of embedded
applications. It is ideal for code shadowing, XIP, and data storage.
Document Number: 001-98282 Rev. *I
Page 4 of 142
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