AT45DB321F-SHN2B-T datasheet, PDF

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AT45DB321F-SHN2B-T: DescriptionNOR Flash 32Mb, 104MHz, 8-SOIC-W, IND TEMP, 1.65-3.6V, T&R, Binary, 512 Byte; Categorysemiconductor Memory IC NOR flash memory; File Size1MB，76 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT45DB321F-SHN2B-T Overview

NOR Flash 32Mb, 104MHz, 8-SOIC-W, IND TEMP, 1.65-3.6V, T&R, Binary, 512 Byte

AT45DB321F-SHN2B-T Parametric

Parameter Name	Attribute value
Maker	Adesto Technologies
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	SOIC-8
series	AT45DB321F
storage	32 Mbit
maximum clock frequency	85 MHz
Interface Type	SPI
organize	4 M x 8
Data bus width	8 bit
Supply voltage - min.	1.65 V
Supply voltage - max.	3.6 V
Supply current—max.	10 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
Encapsulation	Reel
Factory packaging quantity	2000

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AT45DB321F

Low-Power 32 Mbit, 1.65V - 3.6V SPI Serial DataFlash

Memory with 512/528 Byte Page Size

PRELIMINARY DATASHEET

Features

Single 1.65V - 3.6V supply

Serial Peripheral Interface (SPI) compatible

104 MHz dual and quad SPI I/O

Supports SPI modes 0 and 3 and RapidS

™

operation

Active interrupt Smart Intelligent Host Interface technology

Continuous read capability through entire array

Up to 104 MHz

Low-power read option up to 20 MHz

Clock-to-output time (t

) of 8ns maximum

User configurable page size

512 or 528 bytes per page

Page size can also be factory pre-configured

Two fully independent SRAM data buffers

Flexible programming options

Byte/Page Program: 1 to 512/528 bytes directly into main memory

Buffer Write: Buffer to Main Memory Page Program

Flexible erase options

Page Erase: 512/528 bytes

Block Erase: 4KB for 512/528 byte page size

Sector Erase: 64KB for 512/528 byte page size

Chip Erase: 32-Mbits

Program and Erase Suspend/Resume

Advanced hardware and software data protection features

Individual sector protection and lockdown to make any sector read-only

Sector lockdown disable command to permanently disable a sector

128-byte, One-Time Programmable (OTP) Security Register

64 bytes factory programmed with a unique identifier

64 bytes user programmable

JEDEC Standard Manufacturer and Device ID Read (5-byte sequence)

Low-power dissipation

200nA Ultra-Deep Power-Down current (typical)

9µA Deep Power-Down current (typical @ 1.8V)

20µA Standby current (typical @ 1.8V)

5mA Active Read current (typical at 50MHz) — 7.5 mA @ 85 MHz

Endurance / Data Retention: 100,000 program/erase cycles per page / 20 years

Complies with full industrial temperature range (-40C to +85C) ROHS

Green (Pb/Halide-free/RoHS compliant) packaging options

8-lead SOIC (0.208" wide)

8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

DWF — Die Wafer Form

DS-AT45DB321F–-132A–-09/2018

Description

This data sheet provides information on the AT45DB321F device. The AT45DB321F device allows user’s an upgrade

path from the AT45DB161E device and contains the same page sizes of 512 (binary device) or 528 bytes (standard

device).

The AT45DB321F is a 1.65V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety

of digital voice, image, program code, and data storage applications. The AT45DB321F also supports Dual-I/O, Quad-

I/O, and RapidS serial interface for applications requiring very high speed operation. For the AT45DB321F device, the

memory is organized as 8,192 pages of 512 bytes or 528 bytes each.

In addition to the main memory, the AT45DB321F device contains two independent SRAM buffers of 512/528 bytes.

Interleaving between both buffers can dramatically increases a system's ability to write a continuous data stream. In

addition, the SRAM buffers can be used as additional system scratch pad memory, and E

PROM emulation (bit or byte

alterability) can be easily handled with a self-contained three step read-modify-write operation. One of the SRAM’s can

also be used to store critical data that can be written to the Flash memory in the event of a power failure.

Both devices implement the active status interrupt feature using the

Active Status Interrupt

command (25h). This

command eliminates the need continuously read the status register to determine when the operation has finished.

Rather, the microcontroller need only monitor the value of the MISO pin. Once the operation is finished, the DataFlash

device toggles the MISO pin. Refer to

Section 4.4.6, Active Status Interrupt

for more information.

Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the

DataFlash

uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces

active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and

reduces package size. The device is optimized for use in many commercial and industrial applications where

high-density, low-pin count, low-voltage, and low-power are essential.

To allow for simple in-system re-programmability, the AT45DB321F does not require high input voltages for

programming. The device operates from a single 1.65V to 3.6V power supply for the erase and program and read

operations. The AT45DB321F is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting

of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming and erase cycles are self-timed.

Pin Configurations and Pinouts

Figure 1-1

shows the pinouts for the 44-ball WLSCP package, the 8-lead SOIC package, and the 8-pad UDFN package.

Note that the metal pad on the bottom of the UDFN package is not internally connected to a voltage potential. This pad

can be a “no connect” or connected to GND. Care must be taken to avoid the Metal Pad shorting the PCB tracks.

Figure 1-1.

Pinout

8-lead SOIC

Top View

SCK

RESET

8-pad UDFN

Top View

GND

SCK

RESET

GND

AT45DB321F

DS-AT45DB321F–-132A–-09/2018

Table 1-1. Pin Descriptions

Symbol

Name and Function

Chip Select:

Asserting the CS pin selects the device. When the CS pin is deasserted, the device

is deselected and normally be placed in the standby mode (not Deep Power-Down mode) and

the output pin (SO) is placed in a high-impedance state. When the device is deselected, data is

not accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device does not enter standby mode until the completion of the

operation.

Serial Clock:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always

latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the

falling edge of SCK.

Serial Input (I/O

The SI pin is used to shift data into the device. The SI pin is used for all data input including

command and address sequences. Data on the SI pin is always latched on the rising edge of

SCK.

SI (I/O

)

With the Dual-output and Quad-output Read Array commands, the SI pin becomes an output pin

(I/O0) and, along with other pins, allows two bits (on I/O

1-0

) or four bits (on I/O

3-0

) of data to be

clocked out on every falling edge of SCK. To maintain consistency with SPI nomenclature, the SI

(I/O0) pin will be referenced as SI throughout the document with exception to sections dealing

with the Dual-output and Quad-output Read Array commands in which it will be referenced as

I/O

Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).

Serial Output (I/O

The SO pin is used to shift data out of the device. Data on the SO pin is always clocked out on

the falling edge of SCK.

With the Dual-output and Quad-output Read Array commands, the SO pin becomes an output

pin (I/O

) and, along with other pins, allows two bits (on I/O

1-0

) or four bits (on I/O

3-0

) of data to be

clocked out on every falling edge of SCK. To maintain consistency with SPI nomenclature, the

SO (I/O

) pin will be referenced as SO throughout the document with exception to sections

dealing with the Dual-output and Quad-output Read Array commands in which it is referenced as

I/O

Hardware places the SO pin in the high-impedance state whenever the device is deselected (CS

is deasserted).

Input/

Output

—

Input/

Output

Asserted

State

Type

Low

Input

SCK

—

Input

SO (I/O

)

—

AT45DB321F

DS-AT45DB321F–-132A–-09/2018

Table 1-1. Pin Descriptions

(continued)

Symbol

Name and Function

Write Protect (I/O

When the WP pin is asserted, all sectors specified for protection by the Sector Protection

Enable Sector Protection command has been issued or not. The WP pin functions independently

of the software controlled protection method. After the WP pin goes low, the contents of the

Sector Protection Register cannot be modified.

The WP pin must be driven at all times or pulled-high using an external pull-up resistor.

WP (I/O

)

If a program or erase command is issued to the device while the WP pin is asserted, the device

will simply ignore the command and perform no operation. The device will return to the idle state

once the CS pin has been deasserted. The Enable Sector Protection command and the Sector

Lockdown command, however, will be recognized by the device when the WP pin is asserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will

not be used. However, it is recommended that the WP pin also be externally connected to VCC

whenever possible.

With the Quad-output Read Array command, the WP pin becomes an output pin (I/O

) and,

when used with other pins, allows four bits (on I/O

3-0

) of data to be clocked out on every falling

edge of SCK. The QE bit in the Configuration Register must be set in order for the WP pin to be

used as an I/O data pin.

Reset (I/O

A low state on the reset pin (RESET) terminates the operation in progress and resets the internal

state machine to an idle state. The device remains in the reset condition as long as a low level is

present on the RESET pin. Normal operation can resume once the RESET pin is brought back

to a high level.

RESET (I/O

) With the Quad-output Read Array command, the RESET pin becomes an output pin (I/O

) and,

when used with other pins, allows four bits (on I/O

3-0

) of data to be clocked out on every falling

edge of SCK. The QE bit in the Configuration Register must be set in order for the RESET pin to

be used as an I/O data pin.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature is not utilized, then it is

recommended that the RESET pin be driven high externally.

GND

Device Power Supply:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

Ground:

The ground reference for the power supply. GND should be connected to the system

ground.

—

Power

Ground

Low

Input/

Output

Low

Input/

Output

Asserted

State

Type

AT45DB321F

DS-AT45DB321F–-132A–-09/2018

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