74AHC125PW,112 datasheet, PDF - EEWORLD Datasheet

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74AHC125PW,112: DescriptionBuffers and line drivers QUAD 3-STATE BUS BUF; Categorylogic logic; File Size589KB，16 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74AHC125PW,112 Overview

Buffers and line drivers QUAD 3-STATE BUS BUF

74AHC125PW,112 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Is it Rohs certified?	conform to
Maker	Nexperia
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	14
Manufacturer packaging code	SOT402-1
Reach Compliance Code	compliant
Samacsys Description	74AHC(T)125 - Quad buffer/line driver; 3-state@en-us
series	HC/UH
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	5 mm
Logic integrated circuit type	BUS DRIVER
Humidity sensitivity level	1
Number of digits	1
Number of functions	4
Number of ports	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	14.5 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm
Base Number Matches	1

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74AHC125; 74AHCT125

Quad buffer/line driver; 3-state

Rev. 04 — 11 January 2008

Product data sheet

1. General description

The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard JESD7-A.

The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state

outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH

at nOE causes the outputs to assume a high-impedance OFF-state.

The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active

LOW enable inputs.

2. Features

Balanced propagation delays

All inputs have a Schmitt-trigger action

Inputs accepts voltages higher than V

For 74AHC125 only: operates with CMOS input levels

For 74AHCT125 only: operates with TTL input levels

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74AHC125D

74AHCT125D

74AHC125PW

74AHCT125PW

74AHC125BQ

74AHCT125BQ

−40 °C

to +125

°C

−40 °C

to +125

°C

TSSOP14

−40 °C

to +125

°C

Name

SO14

Description

plastic small outline package; 14 leads;

body width 3.9 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT108-1

SOT402-1

SOT762-1

Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5

0.85 mm

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