DATASHEET
HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH
Rad-Hard 16 Channel BiCMOS Analog Multiplexer with High-Z Analog Input
Protection
The HS-1840ARH, HS-1840AEH, HS-1840BRH and HS-1840BEH
are radiation hardened, monolithic 16 channel multiplexers
constructed with the Intersil Rad-Hard Silicon Gate, bonded wafer,
Dielectric Isolation process. They are designed to provide a high input
impedance to the analog source if device power fails (open), or the
analog signal voltage inadvertently exceeds the supply by up to
35V,
regardless of whether the device is powered on or off. Excellent for
use in redundant applications, since the secondary device can be
operated in a standby unpowered mode affording no additional
power drain. More significantly, a very high impedance exists
between the active and inactive devices preventing any interaction.
One of sixteen channel selections is controlled by a 4-bit binary
address plus an Enable-Inhibit input which conveniently controls the
ON/OFF operation of several multiplexers in a system. All inputs have
electrostatic discharge protection. The HS-1840ARH, HS-1840AEH,
HS-1840BRH and HS-1840BEH are processed and screened in full
compliance with MIL-PRF-38535 and QML standards. The devices
are available in a 28 Ld SBDIP and a 28 Ld Ceramic Flatpack.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are contained in
SMD
5962-95630.
FN4355
Rev 6.00
May 23, 2013
Features
• Electrically screened to SMD #
5962-95630
• QML qualified per MIL-PRF-38535 requirements
• Pin-to-pin for Intersil’s HS-1840RH and HS-1840/883S
• Improved radiation performance
- Gamma dose () 3x10
5
RAD(Si)
• Improved r
DS(ON)
Linearity
• Improved access time 1.5µs (Max) over temp and post rad
• High analog input impedance 500Mduring power loss (open)
•
35V
input overvoltage protection (power on or off)
• Dielectrically isolated device islands
• Excellent in Hi-Rel redundant systems
• Break-before-make switching
• No latch-up
Pin Configuration
HS1-1840ARH, HS1-1840AEH, HS1-1840BRH,
HS1-1840BEH
(28 LD SBDIP) CDIP2-T28
TOP VIEW
+V
S
1
NC 2
NC 3
IN 16 4
IN 15 5
IN 14 6
IN 13 7
IN 12 8
IN 11
9
28 OUT
27 -V
S
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
20 IN 2
19 IN 1
18 ENABLE
17 ADDR A0
16 ADDR A1
15 ADDR A2
HS9-1840ARH, HS9-1840AEH, HS9-1840BRH, HS9-1840BEH
(28 LD FLATPACK) CDFP3-F28
TOP VIEW
+V
S
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
(+5V
S
) V
REF
ADDR A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
-V
S
IN 8
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
ENABLE
ADDR A0
ADDR A1
ADDR A2
IN 10 10
IN 9 11
GND 12
(+5V
S
) V
REF
13
ADDR A3 14
FN4355 Rev 6.00
May 23, 2013
Page 1 of 7
HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH
Burn-In/Life Test Circuits
R
+V
S
R
1
2
3
4
5
6
7
8
9
10
GND
F4
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
F1
F2
F3
F5
GND
V
R
R
-V
S
+V
S
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
-V
S
R
R
NOTE:
V
S
+ = +15.5V ±0.5V, V
S
- = -15.5V ±0.5V.
R = 1kΩ ±5%.
C
1
= C
2
= 0.01µF ±10%, 1 EACH PER SOCKET, MINIMUM.
D
1
= D
2
= 1N4002, 1 EACH PER BOARD, MINIMUM.
INPUT SIGNALS:
SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK ±10%.
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.
NOTE:
R = 1kΩ ±5%, 1/4W.
C
1
= C
2
= 0.01µF MINIMUM, 1 EACH PER SOCKET, MINIMUM.
V
S
+ = 15.5V ±0.5V, V
S
- = -15.5V ±0.5V, V
R
= 15.5 ±0.5V
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
FIGURE 2. .STATIC BURN-IN TEST CIRCUIT
Irradiation Circuit
HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH
+15V
NC
NC
+1V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+5V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-15V
1k
NOTE:
3. All irradiation testing is performed in the 28 lead CERDIP package.
FN4355 Rev 6.00
May 23, 2013
Page 4 of 7
HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH
Die Characteristics
DIE DIMENSIONS:
(2820µmx4080µm x 483µm
25.4m)
111 milsx161 milsx19 mils
1
mil
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8.0k
Å
1k
Å
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
Å
2k
Å
Backside Finish:
Silicon
ADDITIONAL INFORMATION:
Worst Case Current Density:
Modified SEM
Transistor Count:
407
Process:
Radiation Hardened Silicon Gate,
DI Wafer, Dielectric Isolation
Metallization Mask Layout
HS-1840ARH, HS-1840BRH
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN8
ENABLE
A0
-V
A1
OUT
A2
+V
A3
V
REF
IN16
GND
IN15
IN14
IN13
IN12
FN4355 Rev 6.00
May 23, 2013
IN10
IN11
IN9
Page 5 of 7
Embedded System
京公网安备 11010802033920号
EEWORLD
