S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8-Volt only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
Notice to Readers:
This document states the current technical specifications
regarding the Spansion product(s) described herein. Spansion LLC deems the
products to have been in sufficient production volume such that subsequent
versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered
may occur.
Publication Number
S29NS-J_01
Revision
A
Amendment
10
Issue Date
March 22, 2006
D a t a
S h e e t
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a doc-
ument with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-
tion content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
uct life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V
IO
range. Changes
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S29NS-J
S29NS-J_01_A10 March 22, 2006
D a t a
S h e e t
Table Of Contents
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .......................................................................................ii
Preliminary ..........................................................................................................ii
Combination .......................................................................................................ii
Full Production (No Designation on Document) ...................................ii
Simultaneous Read/Write Operations with Zero Latency ......................2
Figure 1. Program Operation ............................................... 38
Chip Erase Command Sequence ................................................................... 38
Sector Erase Command Sequence ................................................................ 39
Accelerated Sector Group Erase .............................................................. 39
Table 14. Accelerated Sector Erase Groups, S29NS128J
Table 15. Accelerated Sector Erase Groups, S29NS064J
Table 16. Accelerated Sector Erase Groups, S29NS032J
Table 17. Accelerated Sector Erase Groups, S29NS016J
......... 40
......... 40
......... 41
......... 41
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of Simultaneous Operation Circuit
5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12
Valid Combinations .............................................................................................13
Erase Suspend/Erase Resume Commands .................................................. 42
Figure 2. Erase Operation ................................................... 43
Table 18. Command Definitions .......................................... 44
DQ7: Data# Polling ............................................................................................ 45
Figure 3. Data# Polling Algorithm ........................................ 46
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 14
Table 1. Device Bus Operations ........................................... 14
RDY: Ready ...........................................................................................................47
DQ6: Toggle Bit I ............................................................................................... 47
DQ2: Toggle Bit II .............................................................................................. 47
Figure 4. Toggle Bit Algorithm ............................................. 48
Table 19. DQ6 and DQ2 Indications ..................................... 49
Requirements for Asynchronous Read Operation (Non-Burst) .......... 14
Requirements for Synchronous (Burst) Read Operation ....................... 14
Continuous Burst .............................................................................................15
8-, 16-, and 32-Word Linear Burst with Wrap Around .......................15
Table 2. Burst Address Groups ............................................ 16
Reading Toggle Bits DQ6/DQ2 .....................................................................49
DQ5: Exceeded Timing Limits ........................................................................49
DQ3: Sector Erase Timer ................................................................................50
Table 20. Write Operation Status ......................................... 50
Figure 5. Maximum Negative Overshoot Waveform ................ 51
Figure 6. Maximum Positive Overshoot Waveform.................. 51
8-, 16-, and 32-Word Linear Burst without Wrap Around ................ 16
Programmable Wait State ................................................................................ 16
Handshaking Feature ......................................................................................17
Simultaneous Read/Write Operations with Zero Latency .....................17
Writing Commands/Command Sequences ..................................................17
Accelerated Program Operation ................................................................17
Autoselect Functions ......................................................................................17
Standby Mode ........................................................................................................17
Automatic Sleep Mode ...................................................................................... 18
RESET#: Hardware Reset Input ..................................................................... 18
V
CC
Power-up and Power-down Sequencing ........................................ 18
Output Disable Mode ........................................................................................ 18
Hardware Data Protection .............................................................................. 18
WP# Boot Sector Protection ......................................................................... 19
Low VCC Write Inhibit ................................................................................ 19
Write Pulse “Glitch” Protection ................................................................ 19
Logical Inhibit ................................................................................................... 19
Operating Ranges ................................................................................................ 51
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 7. Test Setup .......................................................... 53
Table 21. Test Specifications ............................................... 53
Key to Switching Waveforms . . . . . . . . . . . . . . . 53
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 53
Figure 8. Input Waveforms and Measurement Levels.............. 53
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54
V
CC
Power-up ..................................................................................................... 54
CLK Characterization ....................................................................................... 55
Figure 9. V
CC
Power-up Diagram.......................................... 54
Figure 10. CLK Characterization........................................... 55
Synchronous/Burst Read .................................................................................. 56
Figure 11. Burst Mode Read (66 and 54 MHz)........................ 56
Figure 12. Burst Mode Read (40 MHz) .................................. 57
Common Flash Memory Interface (CFI) . . . . . . 20
Table 3. CFI Query Identification String ................................ 20
Table 4. System Interface String ......................................... 20
Table 5. Device Geometry Definition .................................... 21
Table 6. Primary Vendor-Specific Extended Query ................. 21
Table 7. Sector Address Table, S29NS128J ........................... 23
Table 8. Sector Address Table, S29NS064J ........................... 27
Table 9. Sector Address Table, S29NS032J ........................... 31
Table 10. Sector Address Table, S29NS016J ......................... 32
Asynchronous Read ........................................................................................... 58
Figure 13. Asynchronous Mode Read .................................... 58
Figure 14. Reset Timings .................................................... 59
Erase/Program Operations ..............................................................................60
Figure 15. Program Operation Timings ................................. 61
Figure 16. Chip/Sector Erase Operations............................... 62
Figure 17. Accelerated Unlock Bypass Programming Timing..... 63
Figure 18. Data# Polling Timings (During Embedded Algorithm) ...
64
Figure 19. Toggle Bit Timings (During Embedded Algorithm) ... 64
Figure 20. 8-, 16-, and 32-Word Linear Burst Address Wrap Around
65
Figure 21. Latency with Boundary Crossing ........................... 65
Figure 22. Initial Access at 3Eh with Address Boundary Latency 66
Figure 23. Example of Extended Valid Address Reducing Wait State
Usage .............................................................................. 66
Figure 24. Back-to-Back Read/Write Cycle Timings ................ 67
Command Definitions ........................................................................................33
Reading Array Data ............................................................................................33
Set Configuration Register Command Sequence ......................................34
Table 11. Burst Modes ....................................................... 34
Handshaking Feature .....................................................................................34
Table 12. Wait States for Handshaking ................................. 35
Sector Lock/Unlock Command Sequence ...................................................35
Reset Command ..................................................................................................35
Autoselect Command Sequence ....................................................................36
Table 13. Autoselect Device ID ............................................ 36
BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 68
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 69
S29NS128J ..............................................................................................................69
VDC048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 10 x
Program Command Sequence ........................................................................36
Unlock Bypass Command Sequence .........................................................37
March 22, 2006 S29NS-J_01_A10
S29NS-J
iii
D a t a
S h e e t
11 mm Package ................................................................................................ 69
S29NS064J ............................................................................................................ 70
VDD044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x
8 mm Package ................................................................................................. 70
S29NS032J and S29NS016J .................................................................................71
VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 7.7 x
6.2 mm Package ................................................................................................71
Table 22. Daisy Chain Part for 128Mbit 110 nm Flash Products
(VDC048, 10 x 11 mm) ...................................................... 72
Table 23. VDC048 Package Information ................................ 72
Table 24. VDC048 Connections ........................................... 72
Figure 25. VDC048 Daisy Chain Layout
(Top View, Balls Facing Down) ............................................. 73
(VDD044, 9.2 x 8 mm) ....................................................... 74
Table 26. VDD044 Package Information ................................ 74
Table 27. VDD044 Connections ............................................ 74
Figure 26. VDD044 Daisy Chain Layout
(Top View, Balls Facing Down) ............................................ 75
Appendix C: Daisy Chain Information . . . . . . . . . 76
Table 28. Daisy Chain Part for 32 and 16 Mbit 110 nm Flash Prod-
ucts (VDE044, 7.7 x 6.2 mm) .............................................. 76
Table 29. VDE044 Package Information ................................ 76
Table 30. VDE044 Connections ............................................ 76
Figure 27. VDE044 Daisy Chain Layout
(Top View, Balls Facing Down) ............................................ 77
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix B: Daisy Chain Information . . . . . . . . .74
Table 25. Daisy Chain Part for 64Mbit 110 nm Flash Products
iv
S29NS-J
S29NS-J_01_A10 March 22, 2006
S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
Distinctive Characteristics
Single 1.8 volt read, program and erase
(1.7 to 1.95 V)
Multiplexed Data and Address for reduced
I/O count
— A15–A0 multiplexed as DQ15–DQ0
— Addresses are latched by AVD# control input when
CE# low
Sector Protection
— Software command sector locking
— WP# protects the two highest sectors
— All sectors locked when A
cc
= V
IL
Handshaking feature
— Provides host system with minimum possible latency
by monitoring RDY
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
Read access times at 66/54 MHz (C
L
=30 pF)
— Burst access times of 11/13.5 ns
at industrial temperature range
— Asynchronous random access times
of 65/70 ns
— Synchronous random access times
of 71/87.5 ns
Supports Common Flash Memory Interface
(CFI)
Software command set compatible with
JEDEC 42.4 standards
— Backwards compatible with Am29F and Am29LV
families
Manufactured on 110 nm process technology
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
Burst Modes
— Continuous linear burst
— 8/16/32 word linear burst with wrap around
— 8/16/32 word linear burst without wrap around
Data# Polling and toggle bits
— Provides a software method of detecting program and
erase operation completion
Power dissipation (typical values, 8 bits
switching, C
L
= 30 pF)
— Burst Mode Read: 25 mA
— Simultaneous Operation: 40 mA
— Program/Erase: 15 mA
— Standby mode: 9 µA
Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
Sector Architecture
— Four 8 Kword sectors
— Two hundred fifty-five (S29NS128J), one hundred
twenty-seven (S29NS064J),sixty-three
(S29NS032J), or thirty-one (S29NS016J) 32 Kword
sectors
— Four banks (see next page for sector count and size)
CMOS compatible inputs and outputs
Package
— 48-ball Very Thin FBGA (S29NS128J)
— 44-ball Very Thin FBGA (S29NS064J, S29NS032J,
S29NS016J)
Cycling Endurance: 1 million cycles per sector
typical
Data Retention: 20 years typical
Publication Number
S29NS-J_00
Revision
A
Amendment
10
Issue Date
March 22, 2006
Analogue and Mixed Signal
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