— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
Flexible Bank architecture
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
Manufactured on 0.13 µm process technology
SecSi™ (Secured Silicon) Sector: Extra 256 Byte
sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function.
—
Customer lockable:
One-time programmable only.
Once locked, data cannot be changed
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
Compatible with JEDEC standards
— Pinout and software compatible with single-power-
supply flash standard
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
Cycling Endurance: 1 million cycles per sector
typical
Data Retention: 20 years typical
PRELIMINARY
Software Features
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
— Suspends erase operations to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation.
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
Sector protection
— Hardware method to prevent any program or erase
operation within a sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
Package options
63-ball Fine Pitch BGA
48-pin TSOP
Performance Characteristics
High performance
— Access time as fast as 55 ns
— Program time: 4 µs/word typical using accelerated
programming function
Publication Number
S29JL064H
Revision
A
Amendment
1
Issue Date
March 26, 2004
This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the
right to change or discontinue work on this proposed product without notice.
P r e l i m i n a r y
General Description
The S29JL064H is a 64 megabit, 3.0 volt-only flash memory device, organized as
4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode
data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device
is designed to be programmed in-system with the standard 3.0 volt V
CC
supply,
and can also be programmed in standard EPROM programmers.
The device is available with an access time of 55, 60, 70, or 90 ns and is offered
in 48-pin TSOP and 63-ball Fine Pitch BGA packages. Standard control pins—chip
enable (CE#), write enable (WE#), and output enable (OE#)—control normal
read and write operations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power supply
for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into
four banks,
two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed,
system software can be used to form user-defined bank groups.
During an Erase/Program operation, any of the three non-busy banks may be
read from. Note that only two banks can operate simultaneously. The device can
improve overall system performance by allowing a host system to program or
erase in one bank, then immediately and simultaneously read from the other
bank, with zero latency. This releases the system from waiting for the completion
of program or erase operations.
The S29JL064H can be organized as both a top and bottom boot sector
configuration.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
8 Mb
24 Mb
24 Mb
8 Mb
Sector Sizes
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
Forty-eight 64 Kbyte/32 Kword
Forty-eight 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
S29JL064H Features
The
SecSi™ (Secured Silicon) Sector
is an extra 256 byte sector capable of
being permanently locked by FASL or customers. The SecSi Customer Indicator
Bit (DQ6) is permanently set to 1 if the part has been customer locked, perma-
nently set to 0 if the part has been factory locked, and is 0 if customer lockable.
This way, customer lockable parts can never be used to replace a factory locked
part.
Factory locked parts provide several options. The SecSi Sector may store a se-
cure, random 16 byte ESN (Electronic Serial Number), customer code
(programmed through Spansion programming services), or both. Customer Lock-
able parts may utilize the SecSi Sector as bonus space, reading and writing like
any other flash sector, or may permanently lock their own code there.
2
S29JL064H
S29JL064HA1 March 26, 2004
P r e l i m i n a r y
DMS (Data Management Software)
allows systems to easily take advantage
of the advanced architecture of the simultaneous read/write product line by al-
lowing removal of EEPROM devices. DMS will also allow the system software to
be simplified, as it will perform all functions necessary to modify data in file struc-
tures, as opposed to single-byte modifications. To write or update a particular
piece of data (a phone number or configuration data, for example), the user only
needs to state which piece of data is to be updated, and where the updated data
is located in the system. This is an advantage compared to systems where user-
written software must keep track of the old data location, status, logical to phys-
ical translation of the data onto the Flash memory device (or memory devices),
and more. Using DMS, user-written software does not need to interface with the
Flash memory directly. Instead, the user's software accesses the Flash memory
by calling one of only six functions.
The device offers complete compatibility with the
JEDEC 42.4 sin-
gle-power-supply Flash command set standard.
Commands are written to
the command register using standard microprocessor write timings. Reading data
out of the device is similar to reading from other Flash or EPROM devices.
The host system can detect whether a program or erase operation is complete by
using the device
status bits:
RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2
(toggle bits). After a program or erase cycle has been completed, the device au-
tomatically returns to the read mode.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The
hardware sector
protection
feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the
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