GS82583ED36GK-625 datasheet, PDF

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GS82583ED36GK-625: DescriptionStatic random access memory 1.2/1.5V 8M x 36 288M; Categorysemiconductor Memory IC Static random access memory; File Size298KB，26 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS82583ED36GK-625 Overview

Static random access memory 1.2/1.5V 8M x 36 288M

GS82583ED36GK-625 Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Product Category	static random access memory
storage	288 Mbit
organize	8 M x 36
maximum clock frequency	625 MHz
Interface Type	Parallel
Supply voltage - max.	1.35 V
Supply voltage - min.	1.25 V
Minimum operating temperature	0 C
Maximum operating temperature	+ 85 C
Installation style	SMD/SMT
Package/box	BGA-260
Encapsulation	Tray
storage type	QDR-III
series	GS82583ED36GK
type	SigmaQuad-IIIe B4
Factory packaging quantity	10

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GS82583ED18/36GK-675/625/550/500

260-Pin BGA

Commercial Temp

Industrial Temp

Features

•

8Mb x 36 and 16Mb x 18 organizations available

675 MHz maximum operating frequency

675 MT/s peak transaction rate (in millions per second)

97 Gb/s peak data bandwidth (in x36 devices)

Separate I/O DDR Data Buses

Non-multiplexed SDR Address Bus

One operation - Read or Write - per clock cycle

Burst of 4 Read and Write operations

3 cycle Read Latency

1.3V nominal core voltage

1.2V, 1.3V, or 1.5V HSTL I/O interface

Configurable ODT (on-die termination)

ZQ pin for programmable driver impedance

ZT pin for programmable ODT impedance

IEEE 1149.1 JTAG-compliant Boundary Scan

260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-

compliant BGA package

288Mb SigmaQuad-IIIe™

Burst of 4 SRAM

Up to 675 MHz

1.3V V

1.2V, 1.3V, or 1.5V V

DDQ

Clocking and Addressing Schemes

The GS82583ED18/36GK SigmaQuad-IIIe SRAMs are

synchronous devices. They employ three pairs of positive and

negative input clocks; one pair of master clocks, CK and CK,

and two pairs of write data clocks, KD[1:0] and KD[1:0]. All

six input clocks are single-ended; that is, each is received by a

dedicated input buffer.

CK and CK are used to latch address and control inputs, and to

control all output timing. KD[1:0] and KD[1:0] are used solely

to latch data inputs.

Each internal read and write operation in a SigmaQuad-IIIe B4

SRAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-IIIe B4 SRAM is always two address

pins less than the advertised index depth (e.g. the 16M x 18 has

4M addressable index).

SigmaQuad-IIIe™ Family Overview

SigmaQuad-IIIe SRAMs are the Separate I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

SRAMs. Although very similar to GSI's second generation of

networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),

these third generation devices offer several new features that

help enable significantly higher performance.

Parameter Synopsis

Speed Grade

-675

-625

-550

-500

Max Operating Frequency

675 MHz

625 MHz

550 MHz

500 MHz

Read Latency

3 cycles

1.25V to 1.35V

Rev: 1.07 12/2017

1/26

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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