PIC32MX564F128LT-V/PF datasheet, PDF

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PIC32MX564F128LT-V/PF: Description32-bit microcontroller - MCU 128KB/32KB USB OTG 80 MHZ 10-B ADC DMA; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，441 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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PIC32MX564F128LT-V/PF Overview

32-bit microcontroller - MCU 128KB/32KB USB OTG 80 MHZ 10-B ADC DMA

PIC32MX564F128LT-V/PF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	TFQFP,
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	50 MHz
DAC channel	NO
DMA channel	YES
External data bus width
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
Number of I/O lines	83
Number of terminals	100
On-chip program ROM width	8
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
ROM programmability	FLASH
Filter level	AEC-Q100; TS 16949
Maximum seat height	1.2 mm
speed	80 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	2.3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

User Manual

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PIC32MX5XX/6XX/7XX

32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)

with

Graphics Interface, USB, CAN, and Ethernet

Operating Conditions

• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz

Timers/Output Compare/Input Capture

• Five General Purpose Timers:

- Five 16-bit and up to two 32-bit Timers/Counters

• Five Output Compare (OC) modules

• Five Input Capture (IC) modules

• Real-Time Clock and Calendar (RTCC) module

Core: 80 MHz/105 DMIPS MIPS32

M4K

• MIPS16e

mode for up to 40% smaller code size

• Code-efficient (C and Assembly) architecture

• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply

Clock Management

•

0.9% internal oscillator (on some variants)

Programmable PLLs and oscillator clock sources

Fail-Safe Clock Monitor (FSCM)

Independent Watchdog Timer

Fast wake-up and start-up

Communication Interfaces

• USB 2.0-compliant Full-Speed OTG controller

• 10/100 Mbps Ethernet MAC with MII and RMII interface

• CAN module:

- 2.0B Active with DeviceNet™ addressing support

• Six UART modules (20 Mbps):

- Supports LIN 2.1 protocols and IrDA

support

• Up to four 4-wire SPI modules (25 Mbps)

• Up to five I

C modules (up to 1 Mbaud) with SMBus

support

• Parallel Master Port (PMP)

Power Management

•

Low-power management modes (Sleep and Idle)

Integrated Power-on Reset, Brown-out Reset

0.5 mA/MHz dynamic current (typical)

41 µA IPD current (typical)

Direct Memory Access (DMA)

• Up to eight channels of hardware DMA with automatic

data size detection

• 32-bit Programmable Cyclic Redundancy Check (CRC)

• Six additional channels dedicated to USB, Ethernet and

CAN modules

Graphics Features

• External graphics interface with up to 34 Parallel Master

Port (PMP) pins:

- Interface to external graphics controller

- Capable of driving LCD directly with DMA and

internal or external memory

Input/Output

• 15 mA or 10 mA source/sink for standard V

and

up to 22 mA for non-standard V

OH1

• 5V-tolerant pins

• Selectable open drain and pull-ups

• External interrupts

Analog Features

• ADC Module:

- 10-bit 1 Msps rate with one Sample and Hold (S&H)

- 16 analog inputs

- Can operate during Sleep mode

• Flexible and independent ADC trigger sources

• Comparators:

- Two dual-input Comparator modules

- Programmable references with 32 voltage points

Qualification and Class B Support

• AEC-Q100 REVH (Grade 2 -40ºC to +105ºC)

• Class B Safety Library, IEC 60730

Debugger Development Support

•

In-circuit and in-application programming

4-wire MIPS

Enhanced JTAG interface

Unlimited program and six complex data breakpoints

IEEE 1149.2-compatible (JTAG) boundary scan

TFBGA

100

0.50

14x14x1

121

0.80

10x10x1.1

VTLA

124

0.50

9x9x0.9

Packages

Type

Pin Count

I/O Pins (up to)

Contact/Lead Pitch

Dimensions

Note:

QFN

0.50

9x9x0.9

0.50

10x10x1

TQFP

100

0.40

12x12x1

All dimensions are in millimeters (mm) unless specified.



2009-2016 Microchip Technology Inc.

DS60001156J-page 1

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