Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 5
Chapter 2. Functional Description ........................................................................................................ 6
Block Diagram....................................................................................................................................................... 6
Gamma Correction Equation................................................................................................................................. 6
Filling the Gamma LUT ......................................................................................................................................... 7
Multi-Color Plane/Channel Mapping ..................................................................................................................... 7
Dynamically Loadable Gamma LUTs.................................................................................................................... 8
Handshake I/O Ports............................................................................................................................................. 8
Signal Descriptions ............................................................................................................................................... 8
Interfacing with the Gamma Corrector .................................................................................................................. 9
Parallel and Sequential Architectures .......................................................................................................... 9
Valid Output ................................................................................................................................................. 9
Timing Specifications .......................................................................................................................................... 10
Parallel Architecture Timing ....................................................................................................................... 10
Sequential Architecture Timing .................................................................................................................. 11
Dynamically Loadable Gamma LUT Timing............................................................................................... 12
Chapter 3. Parameter Settings ............................................................................................................ 14
Configuration Tab................................................................................................................................................ 14
Implementation Tab ............................................................................................................................................ 15
Configuring the Gamma Corrector IP.................................................................................................................. 16
Chapter 4. IP Core Generation............................................................................................................. 17
Licensing the IP Core.......................................................................................................................................... 17
Getting Started .................................................................................................................................................... 17
Configuring Gamma Corrector Core in IPexpress ..................................................................................... 17
Configuring Gamma Corrector Core in Clarity Designer............................................................................ 18
IPexpress-Created Files and Top-Level Directory Structure...................................................................... 21
Clarity Designer-Created Files and IP Top Level Directory Structure........................................................ 22
Instantiating the Core ................................................................................................................................. 23
Running Functional Simulation .................................................................................................................. 23
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 24
Hardware Evaluation........................................................................................................................................... 24
Enabling Hardware Evaluation................................................................................................................... 24
Updating/Regenerating the IP Core .................................................................................................................... 25
Regenerating an IP Core in IPexpress....................................................................................................... 25
Regenerating/Recreating the IP Core in Clarity Designer................................................................................... 26
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 26
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 26
Chapter 5. Support Resources ............................................................................................................ 27
Lattice Technical Support.................................................................................................................................... 27
Lattice Technical Support.................................................................................................................................... 27
E-mail Support ........................................................................................................................................... 27
Local Support ............................................................................................................................................. 27
Internet ....................................................................................................................................................... 27
References.......................................................................................................................................................... 27
Revision History .................................................................................................................................................. 27
Appendix A. Resource Utilization ....................................................................................................... 28
ECP5 Devices ..................................................................................................................................................... 29
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Gamma Corrector IP Core User Guide
Chapter 1:
Introduction
Gamma correction is a type of pre-distortion correction made to images or video frames to offset the non-linear
behavior of display systems, such as cathode ray tube (CRT) displays. A characteristic of CRT displays is that the
intensity they generate is not a linear function of the input voltage. Instead, the intensity is proportional to a power
of the signal amplitude, also referred to as gamma. Gamma is usually greater than 1 and therefore the displays
have a lower gain at low intensities and progressively larger gain at higher intensities. The Gamma Corrector IP
core multiplies the input signal with the inverse of the display transfer function which results in a linear intensity
response with respect to the original input signal.
Several gamma correction methods and values are used in television and display systems. Plasma, LCOS (Liquid
Crystal on Silicon) and DLP (Digital Light Processing) displays have transfer characteristics that are different from
that of CRT displays. Sometimes the display itself can have linear characteristics, but a gamma transformation
(usually called degamma) may be required because of an earlier gamma correction made to the incoming signal.
The Gamma Corrector IP core is a widely parameterizable, multi-color plane gamma correction system. It can sup-
port almost any custom gamma correction requirement.
Quick Facts
Table 1-1 gives quick facts about the Gamma Corrector IP core.
Table 1-1. Gamma Corrector IP Core Quick Facts
Gamma Corrector IP Core
Sequential Architecture
3 Color Planes
Same Color Planes
FPGA Families Supported
Core
Requirements Minimum Device Required
LFE5U-25F
LFE5UM-25F
LAE5UM-25F
LFE3-17EA
LFXP2-5E
27
3
113
57
33
3
113
57
27
3
113
57
Parallel Architecture
3 Color Planes
Same Color Planes
LFE5U-25F
LFE5UM-25F
LAE5UM-25F
LFE3-17EA
LFXP2-5E
36
9
265
133
39
9
265
133
36
9
265
133
Lattice Diamond 3.4
Synopsys
®
Synplify Pro™ for Lattice J-2014.09L
Lattice Synthesis Engine
Aldec
®
Active-HDL™ 9.3 SP2 Lattice Edition II
Mentor Graphics
®
ModelSim™ SE 6.6
®
Sequential Architecture
3 Color Planes
Different Color Planes
LFE5U-25F
LFE5UM-25F
LAE5UM-25F
LFE3-17EA
LFXP2-5E
24
3
104
52
30
3
104
52
24
3
104
52
ECP5™, LatticeECP3™, LatticeXP2™
LUTs
ECP5
EBRs
Registers
Slices
LUTs
Resource
Utilization
LatticeECP3
EBRs
Registers
Slices
LUTs
LatticeXP2
EBRs
Registers
Slices
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
IPUG64_01.3, March 2015
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Gamma Corrector IP Core User Guide
FPGA/CPLD
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