Interlaken (2nd Generation) Intel
®
Stratix
®
10 FPGA IP User Guide
Updated for Intel
®
Quartus
®
Prime Design Suite:
18.1
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UG-20035 | 2018.09.24
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Contents
Contents
1. About this IP Core...........................................................................................................4
1.1.
1.2.
1.3.
1.4.
Features...............................................................................................................4
Device Family Support............................................................................................6
Performance and Resource Utilization....................................................................... 6
Release Information...............................................................................................7
2. Getting Started............................................................................................................... 8
2.1. Installing and Licensing Intel FPGA IP Cores.............................................................. 8
2.1.1. Intel FPGA IP Evaluation Mode.....................................................................9
2.2. Generated File Structure....................................................................................... 11
2.3. Specifying the IP Core Parameters and Options........................................................ 13
2.4. Simulating the IP Core..........................................................................................14
2.5. Compiling the Full Design and Programming the FPGA.............................................. 14
2.6. Integrating Your IP Core in Your Design.................................................................. 15
2.6.1. Pin Assignment........................................................................................15
2.6.2. Adding the External PLL............................................................................ 15
3. Parameter Settings....................................................................................................... 17
4. Functional Description.................................................................................................. 21
4.1. Interfaces........................................................................................................... 21
4.2. IP Core Clocks..................................................................................................... 22
4.3. High Level Data Path Flow.....................................................................................22
4.3.1. Interlaken TX Path................................................................................... 24
4.3.2. Interlaken RX Path................................................................................... 28
4.4. Modes of Operation.............................................................................................. 33
4.4.1. Interleaved and Packet Modes................................................................... 33
4.4.2. Transmit User Data Interface Examples.......................................................33
4.4.3. Receive User Data Interface Example..........................................................37
4.5. IP Core Reset...................................................................................................... 38
4.6. M20K ECC Support...............................................................................................39
4.7. Out-of-Band Flow Control......................................................................................39
4.8. Performance........................................................................................................42
5. Interface Signals.......................................................................................................... 44
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Clock and Reset Interface Signals.......................................................................... 45
Transmit User Interface Signals............................................................................. 46
Receive User Interface Signals...............................................................................48
Management Interface Signals...............................................................................49
Reconfiguration Interface Signals........................................................................... 50
Interlaken Link and Miscellaneous Signals............................................................... 51
External PLL Interface Signals............................................................................... 53
6. Register Map................................................................................................................. 54
7. Test Features................................................................................................................ 57
7.1. Internal Serial Loopback Mode............................................................................... 57
7.2. External Loopback Mode....................................................................................... 58
Interlaken (2nd Generation) Intel
®
Stratix
®
10 FPGA IP User Guide
2
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Contents
8. Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide Archives.................. 59
9. Document Revision History for Interlaken (2nd Generation) Intel Stratix 10 FPGA
IP User Guide ......................................................................................................... 60
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10 FPGA IP User Guide
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1. About this IP Core
Interlaken is a high-speed serial communication protocol for chip-to-chip packet
transfers. The Interlaken (2nd Generation) Intel
®
FPGA IP implements the
Interlaken
Protocol Specification, Revision 1.2.
It supports multiple combinations of number of
lanes (4 to 12) and lane rates from 6.25 gigabits per second (Gbps) to 53.125 Gbps,
on Intel Stratix
®
10 devices, providing raw bandwidth of 25 Gbps to 300 Gbps.
Interlaken provides low I/O count compared to earlier protocols, supporting scalability
in both number of lanes and lane speed. Other key features include flow control, low
overhead framing, and extensive integrity checking. The Interlaken IP core
incorporates a physical coding sublayer (PCS), a physical media attachment (PMA),
and a media access control (MAC) block.
Figure 1.
Typical Interlaken Application
Traffic
Management
Up to
300 Gbps
Interlaken
Interlaken
Interlaken
Interlaken
Switch
Fabric
FPGA/
ASIC
FPGA/
ASIC
Packet
Processing
Up to
300 Gbps
Interlaken
FPGA/
ASIC
To Line
Interface
Ethernet
MAC/Framer
Related Information
•
Interlaken IP Core (2nd Generation) Design Example User Guide
Describes a simulating testbench and a hardware example design that supports
compilation and hardware testing.
Interlaken Protocol Specifications
•
1.1. Features
The Interlaken (2nd Generation) Intel Stratix 10 FPGA IP core has the following
features:
•
•
•
•
•
•
Compliant with the Interlaken Protocol Specification, Revision 1.2.
Supports 4, 6, and 12 serial lanes in configurations that provide up to 318.75
Gbps raw bandwidth.
Supports per-lane data rates of 6.25, 10.3125, 12.5, 25.3, 25.8 and 53.125 Gbps
using Intel FPGA on-chip high-speed transceivers.
Supports dynamically configurable BurstMax and BurstMin values.
Supports Packet mode and Interleaved mode for user data transfer.
Supports up to 256 logical channels in out-of-the-box configuration.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
1. About this IP Core
UG-20035 | 2018.09.24
•
•
•
•
•
Table 1.
Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit
calendar pages.
Supports optional out-of-band flow control blocks.
Supports memory block ECC.
Supports per-lane data rate of 53.125 Gbps using pulse amplitude modulation
(PAM4) mode in Intel Stratix 10 E-Tile variations
Supports per lane data rates of 12.5, 25.3, and 25.8 Gbps using non-return-to-
zero (NRZ) mode in Intel Stratix 10 E-Tile variations.
IP Core Supported Combinations of Number of Lanes and Data Rate
The following combinations are supported in Intel Quartus
®
Prime Pro Edition 18.1
Device
IP Core Supported Combinations
Number of Lanes
4
Intel Stratix 10 L-Tile
12
12
4
6
6
Intel Stratix 10 H-Tile
12
12
12
12
6
6
Lane Rate (Gbps)
6.25
10.3125
12.5
6.25
25.3
25.8
10.3125
12.5
25.3
25.8
25.3
25.8
12.5
25.3
25.8
26.5625
Intel Stratix 10 E-Tile (NRZ)
12
12
12
Intel Stratix 10 E-Tile (PAM4)
12
To obtain 6x53.125 Gbps speed
in PAM4 mode, you must select
Note:
12x26.5625 Gbps combination
in Intel Quartus Prime Pro
Edition 18.1
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Interlaken (2nd Generation) Intel
®
Stratix
®
10 FPGA IP User Guide
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