Data Sheet
FEATURES
Synchronous Buck Controller with
Constant On-Time and Valley Current Mode
ADP1870/ADP1871
TYPICAL APPLICATIONS CIRCUIT
V
IN
= 2.95V TO 20V
VIN
C
C2
Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1871 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged load
Small, 10-lead MSOP and LFCSP packages
C
C
R
TOP
R
C
ADP1870/
ADP1871
COMP/EN BST
C
BST
FB
DRVH
SW
C
IN
V
OUT
Q1
L
V
OUT
R
BOT
GND
C
VREG2
C
OUT
Q2
R
RES
LOAD
VREG
DRVL
PGND
C
VREG
Figure 1.
100
95
90
85
80
75
70
65
60
55
50
45
40 V
IN
= 16.5V (PSM)
V
IN
= 13V (PSM)
T
A
= 25°C
V
OUT
= 1.8V
f
SW
= 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k
LOAD CURRENT (mA)
10k
100k
08730-102
V
IN
= 5V (PSM)
APPLICATIONS
Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies
12 V input POL supplies
EFFICIENCY (%)
V
IN
= 16.5V
V
IN
= 13V
GENERAL DESCRIPTION
The ADP1870/ADP1871 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current-limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
limit, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by utilizing valley
current-mode control architecture. This allows the ADP1870/
ADP1871 to drive all N-channel power stages to regulate output
voltages as low as 0.6 V.
The ADP1871 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1871)
section for more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1870/ADP1871 are well
suited for a wide range of applications that require a single-input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal LDO.
35
30
25
10
100
Figure 2. Efficiency vs. Load Current (V
OUT
= 1.8 V, 300 kHz)
In addition, an internally fixed soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a pre-
charged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced pulse-
width modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1870/ADP1871 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP
and LFCSP packages.
Rev. B
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Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
08730-001
ADP1870/ADP1871
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Applications Circuit............................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Boundary Condition .................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
ADP1870/ADP1871 Block Diagram ............................................ 18
Theory of Operation ...................................................................... 19
Startup .......................................................................................... 19
Soft Start ...................................................................................... 19
Precision Enable Circuitry ........................................................ 19
Undervoltage Lockout ............................................................... 19
On-Board Low Dropout Regulator .......................................... 19
Thermal Shutdown ..................................................................... 20
Programming Resistor (RES) Detect Circuit.......................... 20
Valley Current-Limit Setting .................................................... 20
Hiccup Mode During Short Circuit ......................................... 21
Synchronous Rectifier ................................................................ 22
Data Sheet
Power Saving Mode (PSM) Version (ADP1871).................... 22
Timer Operation ........................................................................ 22
Pseudo-Fixed Frequency ........................................................... 23
Applications Information .............................................................. 24
Feedback Resistor Divider ........................................................ 24
Inductor Selection ...................................................................... 24
Output Ripple Voltage (ΔV
RR
) .................................................. 24
Output Capacitor Selection....................................................... 24
Compensation Network ............................................................ 25
Efficiency Considerations ......................................................... 26
Input Capacitor Selection .......................................................... 27
Thermal Considerations............................................................ 28
Design Example .......................................................................... 29
External Component Recommendations .................................... 31
Layout Considerations ................................................................... 33
IC Section (Left Side of Evaluation Board) ............................. 37
Power Section ............................................................................. 37
Differential Sensing .................................................................... 38
Typical Applications Circuits ........................................................ 39
15 A, 300 kHz High Current Application Circuit .................. 39
5.5 V Input, 600 kHz Application Circuit ............................... 39
300 kHz High Current Application Circuit ............................ 40
Outline Dimensions ....................................................................... 41
Ordering Guide .......................................................................... 42
REVISION HISTORY
7/12—Rev. A to Rev. B
Changed R
ON
= 15 mΩ/100 kΩ Valley Current Level Value from
7.5 to 3.87; Table 7 .......................................................................... 21
Updated Outline Dimensions ................................................................. 41
6/10—Rev. 0 to Rev. A
Added LFCSP Package ....................................................... Universal
Changes to Applications Section .................................................... 1
Changes to Internal Regulator Characteristics Parameter,
Table 1 ............................................................................................ 3
Changes to Table 2 and Table 3........................................................5
Changes to Figure 3 and Table 4......................................................6
Change to Figure 22 ....................................................................... 10
Changes to Figure 65...................................................................... 18
Changes to Efficiency Considerations Section ........................... 26
Changes to Table 9 ..................................................................................... 28
Added Figure 84; Renumbered Sequentially....................................... 28
Added Figure 96 ......................................................................................... 41
Changes to Ordering Guide .................................................................... 42
3/10—Revision 0: Initial Version
Rev. B | Page 2 of 44
Data Sheet
SPECIFICATIONS
ADP1870/ADP1871
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). V
REG
= 5 V,
V
BST
− V
SW
= V
REG
− V
RECT_DROP
(see Figure 40 to Figure 42). V
IN
= 12 V. The specifications are valid for T
J
= −40°C to +125°C,
unless otherwise specified.
Table 1.
Parameter
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range
Symbol
V
IN
Conditions
C
IN
= 22 µF to PGND (at Pin 1)
ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz)
ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz)
ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz)
V
FB
= 1.5 V, no switching
COMP/EN < 285 mV
Rising V
IN
(see Figure 35 for temperature variation)
Falling V
IN
from operational state
VREG should not be loaded externally because it is
intended to only bias internal circuitry.
C
VREG
= 1 µF to PGND, 0.22 µF to GND, V
IN
= 2.95 V to 20 V
ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz)
ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz)
ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz)
V
IN
= 7 V, 100 mA
V
IN
= 12 V, 100 mA
0 mA to 100 mA, V
IN
= 7 V
0 mA to 100 mA, V
IN
= 20 V
V
IN
= 7 V to 20 V, 20 mA
V
IN
= 7 V to 20 V, 100 mA
100 mA out of V
REG
, V
IN
≤ 5 V
V
IN
= 20 V
See Figure 58
V
FB
T
J
= +25°C
T
J
= −40°C to +85°C
T
J
= −40°C to +125°C
V
FB
= 0.6 V, COMP/EN = released
RES = 47 kΩ ± 1%
RES = 22 kΩ ± 1%
RES = none
RES = 100 kΩ ± 1%
Typical values measured at 50% time points with 0 nF
at DRVH and DRVL; maximum values are guaranteed
by bench evaluation
1
2.7
5.5
11
22
Min
Typ
Max
Unit
2.95
2.95
3.25
Quiescent Current
Shutdown Current
Undervoltage Lockout
UVLO Hysteresis
INTERNAL REGULATOR
CHARACTERISTICS
VREG Operational Output Voltage
I
Q_REG
+ I
Q_BST
I
REG,SD
+
I
BST,SD
UVLO
12
12
12
1.1
190
2.65
190
20
20
20
280
V
V
V
mA
μA
V
mV
V
REG
VREG Output in Regulation
Load Regulation
Line Regulation
V
IN
to V
REG
Dropout Voltage
Short VREG to PGND
SOFT START
Soft Start Period
ERROR AMPLIFER
FB Regulation Voltage
2.75
2.75
3.05
4.8
4.8
5
5
5
4.981
4.982
32
33
2.5
2.0
300
229
3.0
600
600
600
496
1
3
6
12
24
5.5
5.5
5.5
5.16
5.16
415
320
V
V
V
V
V
mV
mV
mV
mV
mV
mA
ms
mV
mV
mV
µS
nA
V/V
V/V
V/V
V/V
Transconductance
FB Input Leakage Current
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from DRVL to PGND
G
m
I
FB, Leak
596
594.2
320
604
605.8
670
50
3.3
6.5
13
26
SWITCHING FREQUENCY
ADP1870ARMZ-0.3/
ADP1871ARMZ-0.3 (300 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
300
V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C
V
IN
= 20 V
84% duty cycle (maximum)
1120
1200
146
340
1280
190
400
kHz
ns
ns
ns
Rev. B | Page 3 of 44
ADP1870/ADP1871
Parameter
ADP1870ARMZ-0.6/
ADP1871ARMZ-0.6 (600 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
ADP1870ARMZ-1.0/
ADP1871ARMZ-1.0 (1.0 MHz)
On-Time
Minimum On-Time
Minimum Off-Time
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time
2
Fall Time
2
Low-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time
2
Fall Time
2
Propagation Delays
DRVL Fall to DRVH Rise
2
DRVH Fall to DRVL Rise
2
SW Leakage Current
Integrated Rectifier
Channel Impedance
PRECISION ENABLE THRESHOLD
Logic High Level
Enable Hysteresis
COMP VOLTAGE
COMP Clamp Low Voltage
COMP Clamp High Voltage
COMP Zero Current Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Hiccup Current Limit Timing
1
Data Sheet
Symbol
Conditions
Min
Typ
600
540
82
340
1.0
312
60
340
Max
Unit
kHz
ns
ns
ns
MHz
ns
ns
ns
V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C
V
IN
= 20 V, V
OUT
= 0.8 V
65% duty cycle (maximum)
500
580
110
400
V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C
V
IN
= 20 V
45% duty cycle (maximum)
285
340
85
400
t
r,DRVH
t
f,DRVH
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
V
BST
− V
SW
= 4.4 V, C
IN
= 4.3 nF (see Figure 60)
V
BST
− V
SW
= 4.4 V, C
IN
= 4.3 nF (see Figure 61)
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
V
REG
= 5.0 V, C
IN
= 4.3 nF (see Figure 61)
V
REG
= 5.0 V, C
IN
= 4.3 nF (see Figure 60)
V
BST
− V
SW
= 4.4 V (see Figure 60)
V
BST
− V
SW
= 4.4 V (see Figure 61)
V
BST
= 25 V, V
SW
= 20 V, V
REG
= 5 V
I
SINK
= 10 mA
V
IN
= 2.9 V to 20 V, V
REG
= 2.75 V to 5.5 V
V
IN
= 2.9 V to 20 V, V
REG
= 2.75 V to 5.5 V
245
2.25
0.7
25
11
1.6
0.7
18
16
15.4
18
3
1
Ω
Ω
ns
ns
Ω
Ω
ns
ns
ns
ns
µA
Ω
2.2
1
t
r,DRVL
t
f,DRVL
t
tpdhDRVH
t
tpdhDRVL
I
SWLEAK
110
22
285
37
330
mV
mV
V
V
COMP(low)
V
COMP(high)
V
COMP_ZCT
T
TMSD
From disabled state, release COMP/EN pin to enable
device (2.75 V ≤ V
REG
≤ 5.5 V)
(2.75 V ≤ V
REG
≤ 5.5 V)
(2.75 V ≤ V
REG
≤ 5.5 V)
Rising temperature
0.47
2.55
1.07
155
15
6
V
V
°C
°C
ms
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 60 and Figure 61), C
GATE
= 4.3 nF, and the upper- and lower-side
MOSFETs being Infineon BSC042N03MSG.
2
Not automatic test equipment (ATE) tested.
Rev. B | Page 4 of 44
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VREG to PGND, GND
VIN to PGND
FB, COMP/EN to GND
DRVL to PGND
SW to PGND
BST to SW
BST to PGND
DRVH to SW
PGND to GND
θ
JA
(10-Lead MSOP)
2-Layer Board
4-Layer Board
θ
JA
(10-Lead LFCSP)
4-Layer Board
Operating Junction Temperature
Range
Storage Temperature Range
Soldering Conditions
Maximum Soldering Lead
Temperature (10 sec)
Rating
−0.3 V to +6 V
−0.3 V to +28 V
−0.3 V to (V
REG
+ 0.3 V)
−0.3 V to (V
REG
+ 0.3 V)
−2.0 V to +28 V
−0.6 V to (V
REG
+ 0.3 V)
−0.3 V to 28 V
−0.3 V to V
REG
±0.3
V
213.1°C/W
171.7°C/W
40°C/W
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
300°C
ADP1870/ADP1871
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θ
JA
(10-Lead MSOP)
2-Layer Board
4- Layer Board
θ
JA
(10-Lead LFCSP)
4- Layer Board
1
θ
JA1
213.1
171.7
40
Unit
°C/W
°C/W
°C/W
θ
JA
is specified for the worst-case conditions; that is, θ
JA
is specified for the
device soldered in a circuit board for surface-mount packages.
BOUNDARY CONDITION
In determining the values given in Table 2 and Table 3, natural
convection was used to transfer heat to a 4-layer evaluation board.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.
Rev. B | Page 5 of 44
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