74AUP2G38GN,115 datasheet, PDF

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74AUP2G38GN,115: DescriptionLogic gateLow-Power dual 2-input NAND gate; Categorylogic logic; File Size873KB，21 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74AUP2G38GN,115 Overview

Logic gateLow-Power dual 2-input NAND gate

74AUP2G38GN,115 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	SON
package instruction	SON,
Contacts	8
Manufacturer packaging code	SOT1116
Reach Compliance Code	compliant
Samacsys Description	74AUP2G38 - Low-power dual 2-input NAND gate; open drain@en-us
series	AUP/ULP/V
JESD-30 code	R-PDSO-N8
JESD-609 code	e3
length	1.2 mm
Logic integrated circuit type	NAND GATE
Humidity sensitivity level	1
Number of functions	2
Number of entries	2
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-DRAIN
Package body material	PLASTIC/EPOXY
encapsulated code	SON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	24 ns
Maximum seat height	0.35 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.1 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.3 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	1 mm
Base Number Matches	1

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74AUP2G38

Low-power dual 2-input NAND gate; open drain

Rev. 8 — 11 February 2013

Product data sheet

1. General description

The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output

of the device is an open drain and can be connected to other open-drain outputs to

implement active-LOW wired-OR or active-HIGH wired-AND functions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD78B Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial Power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

74AUP2G38GN,115 Related Products

	74AUP2G38GN,115	74AUP2G38GS,115	74AUP2G38GT,115	74AUP2G38GF,115
Description	Logic gateLow-Power dual 2-input NAND gate	Logic gate NAND 4.6 V 20 mA	Logic gate 1.8V DUAL LP 2-INPT	Logic gateLow-Power dual 2-input NAND gate
Brand Name	Nexperia	Nexperia	Nexperia	Nexperia
Maker	Nexperia	Nexperia	Nexperia	Nexperia
Parts packaging code	SON	SON	SON	SON
package instruction	SON,	VSON,	VSON,	VSON,
Contacts	8	8	8	8
Manufacturer packaging code	SOT1116	SOT1203	SOT833-1	SOT1089
Reach Compliance Code	compliant	compliant	compliant	compliant
Samacsys Description	74AUP2G38 - Low-power dual 2-input NAND gate; open drain@en-us	74AUP2G38 - Low-power dual 2-input NAND gate; open drain@en-us	74AUP2G38 - Low-power dual 2-input NAND gate; open drain@en-us	74AUP2G38 - Low-power dual 2-input NAND gate; open drain@en-us
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V
JESD-30 code	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8
JESD-609 code	e3	e3	e3	e3
length	1.2 mm	1.35 mm	1.95 mm	1.35 mm
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE	NAND GATE
Humidity sensitivity level	1	1	1	1
Number of functions	2	2	2	2
Number of entries	2	2	2	2
Number of terminals	8	8	8	8
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SON	VSON	VSON	VSON
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	260	NOT SPECIFIED
propagation delay (tpd)	24 ns	24 ns	24 ns	24 ns
Maximum seat height	0.35 mm	0.35 mm	0.5 mm	0.5 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	0.8 V	0.8 V	0.8 V	0.8 V
Nominal supply voltage (Vsup)	1.1 V	1.1 V	1.2 V	1.1 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.3 mm	0.35 mm	0.5 mm	0.35 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	30	NOT SPECIFIED
width	1 mm	1 mm	1 mm	1 mm
Base Number Matches	1	1	1	1

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