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74LVC2G241GN,115

Description
Dual buffer line driver 3-state
Categorylogic    logic   
File Size281KB,20 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Download Datasheet Parametric View All

74LVC2G241GN,115 Overview

Dual buffer line driver 3-state

74LVC2G241GN,115 Parametric

Parameter NameAttribute value
Brand NameNexperia
MakerNexperia
Parts packaging codeSON
package instructionSON,
Contacts8
Manufacturer packaging codeSOT1116
Reach Compliance Codecompliant
Samacsys Description74LVC2G241 - Dual buffer/line driver; 3-state@en-us
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-N8
JESD-609 codee3
length1.2 mm
Logic integrated circuit typeBUS DRIVER
Humidity sensitivity level1
Number of digits1
Number of functions2
Number of ports2
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)11 ns
Maximum seat height0.35 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin (Sn)
Terminal formNO LEAD
Terminal pitch0.3 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width1 mm
74LVC2G241
Dual buffer/line driver; 3-state
Rev. 15 — 22 November 2018
Product data sheet
1. General description
The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs
are controlled by the output enable inputs 1OE and 2OE:
A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.
A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall
times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G241 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing a damaging backflow current through the device when it is powered
down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
±24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
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