Dual 1:2, LVDS Output Fanout Buffer
8SLVD2102
Datasheet
Description
The 8SLVD2102 is a high-performance differential dual 1:2 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVD2102 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2102 ideal for those clock distribution applications
demanding well-defined performance and repeatability.
Two independent buffers with two low skew outputs each are
available. The integrated bias voltage generators enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
Two 1:2, low skew, low additive jitter LVDS fanout buffers
Two differential clock inputs
Differential pairs can accept the following differential input
levels: LVDS and LVPECL
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (maximum)
Propagation delay: 300ps (maximum)
Low additive phase jitter: 200fs, RMS (maximum);
f
REF
= 156.25MHz, V
PP
= 1V, V
CMR
= 1V,
Integration Range 10kHz - 20MHz
2.5V supply voltage
Maximum device current consumption (I
DD
): 90mA
Lead-free (RoHS 6) 16-Lead VFQFPN package
-40°C to 85°C ambient operating temperature
Block Diagram
V
DD
Pin Assignment
nQB1
nQB0
14
QB1
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
GND
EN
PCLKB
1
2
3
4
16
15
QB0
13
12
11
nQA1
QA1
nQA0
QA0
8SLVD2102I
V
DD
PCLKB
nPCLKB
QB0
nQB0
QB1
nQB1
8XXXXXX
5
6
7
8
10
9
nPCLKB
PCLKA
V
REF
V
DD
Voltage
Reference
16-pin, 3.0 x 3.0 mm VFQFPN Package
16-pin, 3.0mm x 3.0mm VFQFN Package
EN
8SLVD2102 January 21, 2018
1
nPCLKA
V
REF
©2018 Integrated Device Technology, Inc.
V
DD
8SLVD2102 DATASHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 10
11, 12
13, 14
15, 16
Name
GND
EN
PCLKB
nPCLKB
V
DD
PCLKA
nPCLKA
V
REF
QA0, nQA0
QA1, nQA1
QB0, nQB0
QB1, nQB1
Power
Input
Input
Input
Power
Input
Input
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Power supply ground.
Output enable pin.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Power supply pin.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Bias voltage reference for the PCLKx, nPCLKx inputs.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown
Resistor
Input Pullup
Resistor
Input Pulldown
Resistor
Input Pullup
Resistor
PCLK inputs
PCLK inputs
EN input
EN input
Test Conditions
Minimum
Typical
2
51
51
51
51
Maximum
Units
pF
k
k
k
k
Table 3. EN Input Selection Function Table
Input
EN
0 (Low)
1 (High)
Open
Operation
Outputs are disabled and outputs are static at Qx = 0 (low level) and nQx = 1 (high level).
Bank A outputs are enabled and Bank B outputs are disabled at the following static levels: QBx = 0 (low level) and
nQBx = 1 (high level).
All outputs enabled.
NOTE: EN is an asynchronous control.
8SLVD2102 January 21, 2018
2
©2018 Integrated Device Technology, Inc.
8SLVD2102 DATASHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model; NOTE 1
ESD - Charged Device Model; NOTE 1
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
125C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
All outputs terminated 100
between nQx, Qx
Test Conditions
Minimum
2.375
Typical
2.5
80
Maximum
2.625
90
Units
V
mA
Table 4B. Output Enable (EN) Input DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
MID
V
IH
V
IL
I
IH
I
IL
Parameter
Input Voltage - Open Pin
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Open
0.8 * V
DD
-0.3
Minimum
Typical
V
DD
/ 2
V
DD
+ 0.3
0.2 * V
DD
150
Maximum
Units
V
V
V
µA
µA
8SLVD2102 January 21, 2018
3
©2018 Integrated Device Technology, Inc.
8SLVD2102 DATASHEET
Table 4C. Differential Input Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF_AC
V
PP
V
CMR
Parameter
Input
High Current
Input
Low Current
PCLKA, nPCLKA
PCLKB, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.5V, I
REF
= +100µA
f
REF
< 1.5 GHz
f
REF
> 1.5 GHz
-10
-150
1.00
0.15
0.2
1
1.35
1.6
1.6
V
DD
– V
PP
/2
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
Reference Voltage for Input Bias
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V. V
IH
should be less than V
DD.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Table 4D. LVDS Output DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C°
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
100 termination between nQx, Qx
100 termination between nQx, Qx
100 termination between nQx, Qx
100 termination between nQx, Qx
1.0
Minimum
247
Typical
Maximum
454
50
1.4
50
Units
mV
mV
V
mV
8SLVD2102 January 21, 2018
4
©2018 Integrated Device Technology, Inc.
8SLVD2102 DATASHEET
Table 5. AC Electrical Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
REF
V/t
t
PD
Parameter
Input Frequency
Input Edge Rate
Propagation Delay; NOTE 1
Channel Isolation
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
Output Skew; NOTE 2, 3
Output Bank Skew; NOTE 3
Pulse Skew
Part-to-Part Skew; NOTE 3, 4
f
REF
= 1228.8MHz, V
PP
= 0.2V, V
CMR
= 1V
Integration Range: 10kHz – 20MHz
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
f
REF
= 156.25MHz, V
PP
= 0.5V, V
CMR
= 1V
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz, V
PP
= 1V, V
CMR
= 1V
Integration Range: 10kHz – 20MHz
f
QB0
= 500MHz, V
PP (PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V and
f
QA1
= 62.5MHz, V
PP(PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
f
QB0
= 500MHz, V
PP (PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V and
f
QA1
= 15.625MHz, V
PP (PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
20% to 80%
20
140
80
QA[0:1], nQA[0:1], QB[0:1], nQB[0:1]
Between Outputs within Each Bank
50% Input Duty Cycle, f
REF
= 100MHz
-50
PCLKA, nPCLKA to QA[0:1], nQA[0:1],
PCLKB, nPCLKB to QB[0:1], nQB[0:1]
0.75
100
196
75
14
7
40
15
50
200
50
250
200
300
Test Conditions
Minimum
Typical
Maximum
2
Units
GHz
V/ns
ps
dB
ps
ps
ps
ps
fs
fs
fs
68
dB
t
JIT, SP
Spurious Suppression,
Coupling from QA1 to QB0
74
dB
t
R
/ t
F
Output Rise/ Fall Time
120
200
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
8SLVD2102 January 21, 2018
5
©2018 Integrated Device Technology, Inc.
京公网安备 11010802033920号
EEWORLD
