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SI5380A-BXXXXX-GM: DescriptionClock Generator and Support Products Factory pre-programmed Ultra-low Jitter JESD204B Clock Generator/Jitter Attenuator with: 4-inputs/12-outputs up to 1.47456 GHz; Categorysemiconductor The clock and timer IC The clock generator and supporting products; File Size1MB，54 Pages; ManufacturerSilicon Labs; Websitehttps://www.silabs.com; Environmental Compliance

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SI5380A-BXXXXX-GM Overview

Clock Generator and Support Products Factory pre-programmed Ultra-low Jitter JESD204B Clock Generator/Jitter Attenuator with: 4-inputs/12-outputs up to 1.47456 GHz

SI5380A-BXXXXX-GM Parametric

Parameter Name	Attribute value
Maker	Silicon Labs
Product Category	Clock generators and supporting products
series	Si5380
Encapsulation	Tray
Factory packaging quantity	260

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Si5380 Rev D Data Sheet

Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

The Si5380 is a high performance, integer-based (M/N) clock generator for small cell

applications which demand the highest level of integration and phase noise perform-

ance. Based on Silicon Laboratories’ 4

th

generation DSPLL

™

technology, the Si5380

combines frequency synthesis and jitter attenuation in a highly integrated digital solu-

tion that eliminates the need for external VCXO and loop filter components. A low-cost,

fixed-frequency crystal provides frequency stability for free-run and holdover modes.

This all-digital solution provides superior performance that is highly immune to external

board disturbances such as power supply noise.

KEY FEATURES

• DSPLL eliminates external VCXO and

analog loop filter components

• Supports JESD204B clocking: DCLK and

SYSREF

• Ultra-low jitter of 65 fs

• Input frequency range:

• External Crystal: 54 MHz

• Differential: 11.52 MHz to 737.28 MHz

• LVCMOS: 11.52 MHz to 245.76 MHz

Applications:

• JESD204B clock generation

• Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells

• Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A)

• Remote Radio Head (RRH), wireless repeaters, wireless backhaul

• Data conversion sampling clocks (ADC, DAC, DDC, DUC)

• Output frequency range:

• Differential: 480 kHz to 1.47456 GHz

• LVCMOS: 480 kHz to 245.76 MHz

• Status monitoring

• Hitless switching

• Si5380: 4 input, 12 output, 64-QFN 9×9 mm

54 MHz XTAL

XA

OSC

IN0

4 Input

Clocks

IN1

IN2

÷INT

÷INT

÷INT

÷INT

Delay

DSPLL

Delay

XB

÷INT

÷INT

÷INT

÷INT

÷INT

÷INT

÷INT

÷INT

÷INT

÷INT

Delay

NVM

÷INT

÷INT

OUT0A

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT9A

Device and

System Clocks

Delay

IN3/FB_IN

Delay

Status Flags

I2C / SPI

Status Monitor

Control

Si5380

silabs.com

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Rev. 1.0

Si5380 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5380 is a high performance clock generator that is capable of synthesizing up to 10 unique integer related frequencies at any of

the device’s 12 outputs. The output clocks can be generated in free-run mode or synchronized to any one of the four external inputs.

Clock generation is provided by Silicon Laboratories’ 4th generation DSPLL technology which combines frequency synthesis and jitter

attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. The Si5380

device is fully configurable using the I2C or SPI serial interface and has in-circuit programmable non-volatile memory.

3.1 Frequency Configuration

The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock fre-

quency or free-running XTAL. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-low phase

noise analog 15 GHz VCO, and a user configurable feedback divider. An internal oscillator (OSC) provides the DSPLL with a stable

low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the free-run or holdover modes. The oscillator

simply requires an external, low cost 54 MHz fundamental mode crystal to operate. No other external components are required for fre-

quency generation. A key feature of this DSPLL is that it provides immunity to external noise coupling from power supplies and other

uncontrolled noise sources that normally exist on printed circuit boards.

3.1.1 Si5380 LTE Frequency Configuration

The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.

The combination of flexible integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies

for applications that require ultra-low phase noise and spurious performance. At the core of the device are the N dividers which deter-

mine the number of unique frequencies that can be generated from the device. The table below shows a list of some possible output

frequencies for LTE applications. The Si5380’s DSPLL core can generate up to five unique top frequencies. These frequencies are dis-

tributed to the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10 unique integer-ratio

related frequencies on the Si5380. The ClockBuilder Pro software utility provides a simple means of automatically calculating the opti-

mum divider values (P, M, N and R) for the frequencies listed in the table below.

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Si5380 Rev D Data Sheet

Functional Description

Table 3.1. Example of Possible LTE Clock Frequencies

F

IN

(MHz)

1

15.36

19.20

30.72

38.40

61.44

76.80

122.88

153.60

184.32

245.76

307.20

368.64

491.52

614.40

737.28

—

—

—

LTE Device Clock Frequencies Fout (MHz)

2

15.36

19.20

30.72

38.40

61.44

76.80

122.88

153.60

184.32

245.76

307.20

368.64

491.52

614.40

737.28

983.04

1228.80

1474.56

Note:

1. The Si5380 locks to any one of the frequencies listed in the F

IN

column and generates LTE device clock frequencies.

2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks.

3.1.2 Si5380 Configuration for JESD204B Clock Generation

The Si5380 can be used as a high performance, fully integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete

VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks

(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF

clocks to drive JESD204B converters, FPGAs, or other logic devices. The Si5380 will clock up to four JESD204B targets using four or

more DCLKs and four SYSREF clocks with adjustable delay.Each DCLK is grouped with a SYSREF clock in this configuration.If SYS-

REF clocking is implemented in external logic, then the Si5380 will clock up to 12 JESD204B targets.Not limited to JESD204B applica-

tions, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications. An example

of a JESD204B frequency configuration is shown in the figure below. In this case, the N dividers determine the device clock frequency

and the R dividers provide the divided SYSREF clock which is used as the lower frequency frame clock. The N divider path also in-

cludes a configurable delay path (∆t) for controlling deterministic latency. The example shows a configuration where all the device

clocks are controlled by a single delay path (∆t0) while the SYSREF clocks each have their own independent delay paths (∆t1 – ∆t4),

though other combinations are also possible. Delay is programmable in steps of 68 ps in the range of ±128 steps (±8.6 ns). See the

3.5.14 Output Skew Control (Δt

0

- Δt

4

)

section for details on skew control. The SYSREF clock is always periodic and can be controlled

(on/off) without glitches by enabling or disabling its output through register writes.

silabs.com

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Rev. 1.0 | 4

SI5380A-BXXXXX-GM Related Products

	SI5380A-BXXXXX-GM	SI5380A-B05717-GM	SI5380A-B-GMR
Description	Clock Generator and Support Products Factory pre-programmed Ultra-low Jitter JESD204B Clock Generator/Jitter Attenuator with: 4-inputs/12-outputs up to 1.47456 GHz	Clock generators and supporting productsUltra-Low Phase Noise, Wireless Jitter Attenuating Clock Multiplier	Clock generator and supporting products Base/blank prototyping device: Ultra-low Jitter JESD204B Clock Generator/Jitter Attenuator with: 4-inputs/12-outputs up to 1.47456 GHz
Maker	Silicon Labs	Silicon Labs	Silicon Labs
Product Category	Clock generators and supporting products	Clock generators and supporting products	Clock generators and supporting products
series	Si5380	Si538x	Si5380
Encapsulation	Tray	Tray	Reel
Factory packaging quantity	260	-	1000

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