74LVC1G74GN,115 datasheet, PDF

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74LVC1G74GN,115: DescriptionTriggerD-typ F/F w/set Reset Postrigger; Categorylogic logic; File Size832KB，26 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74LVC1G74GN,115 Overview

TriggerD-typ F/F w/set Reset Postrigger

74LVC1G74GN,115 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	SON
package instruction	SON,
Contacts	8
Manufacturer packaging code	SOT1116
Reach Compliance Code	compliant
Samacsys Description	74LVC1G74 - Single D-type flip-flop with set and reset; positive edge trigger@en-us
series	LVC/LCX/Z
JESD-30 code	R-PDSO-N8
JESD-609 code	e3
length	1.2 mm
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	13.4 ns
Maximum seat height	0.35 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.3 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	1 mm
minfmax	200 MHz

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74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Rev. 13 — 5 December 2016

Product data sheet

1. General description

The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)

inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

outputs.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing damaging backflow current through the device

when it is powered down.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features and benefits



Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant inputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:



JESD8-7 (1.65 V to 1.95 V)



JESD8-5 (2.3 V to 2.7 V)



JESD8-B/JESD36 (2.7 V to 3.6 V)

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V

24

mA output drive (V

= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Specified from

40 C

to +85

C

and

40 C

to +125

C



74LVC1G74GN,115 Related Products

	74LVC1G74GN,115	74LVC1G74GD,125
Description	TriggerD-typ F/F w/set Reset Postrigger	Trigger Flip Flop D-Type Pos-Edge 1-Element
Brand Name	Nexperia	Nexperia
Maker	Nexperia	Nexperia
Parts packaging code	SON	SON
package instruction	SON,	XSON-8
Contacts	8	8
Manufacturer packaging code	SOT1116	SOT996-2
Reach Compliance Code	compliant	compliant
series	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-N8	R-PDSO-N8
JESD-609 code	e3	e4
length	1.2 mm	3 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Humidity sensitivity level	1	1
Number of digits	1	1
Number of functions	1	1
Number of terminals	8	8
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SON	VSON
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)	13.4 ns	13.4 ns
Maximum seat height	0.35 mm	0.5 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1.65 V	1.65 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Tin (Sn)	NICKEL PALLADIUM GOLD
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.3 mm	0.5 mm
Terminal location	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	1 mm	2 mm
minfmax	200 MHz	200 MHz

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