74AHC259; 74AHCT259
8-bit addressable latch
Rev. 02 — 15 May 2008
Product data sheet
1. General description
The 74AHC259; 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC259; 74AHCT259 is a high-speed 8-bit addressable latch designed for general
purpose storage applications in digital systems. It is a multifunctional device capable of
storing single-line data in eight addressable latches and providing a 3-to-8 decoder and
multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates an active
LOW common reset (MR) for resetting all latches as well as an active LOW enable input
(LE).
The 74AHC259; 74AHCT259 has four modes of operation:
•
In the addressable latch mode, data on the data line (D) is written into the addressed
latch. The addressed latch will follow the data input with all non-addressed latches
remaining in their previous states.
•
In the memory mode, all latches remain in their previous states and are unaffected by
the data or address inputs.
•
In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state
of the data input (D) with all other outputs in the LOW state.
•
In the reset mode, all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74AHC259; 74AHCT259 as an address latch, changing more than
one bit of the address could impose a transient-wrong address. Therefore, this should
only be done while in the memory mode.
2. Features
I
I
I
I
I
I
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Inputs accept voltages higher than V
CC
NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
I
Input levels:
N
For 74AHC259: CMOS level
N
For 74AHCT259: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC259
74AHC259D
74AHC259PW
74AHCT259
74AHCT259D
74AHCT259PW
−40 °C
to +125
°C
−40 °C
to +125
°C
SO16
TSSOP16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT403-1
−40 °C
to +125
°C
−40 °C
to +125
°C
SO16
TSSOP16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT403-1
Description
Version
Type number
4. Functional diagram
13
15
14
Z9
G8
G10
9,10D
0
1
C10
8R
DX
14
LE
Q0
13
D
Q1
Q2
Q3
1
2
3
A0
A1
A2
MR
15
mna573
4
1
4
5
6
7
9
10
11
12
2
3
0
G
2
0
7
1
5
6
2
7
3
9
4
10
5
11
6
12
7
mna572
Q4
Q5
Q6
Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
© NXP B.V. 2008. All rights reserved.
74AHC_AHCT259_2
Product data sheet
Rev. 02 — 15 May 2008
2 of 17
NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
Table 2.
Symbol
Q6
Q7
D
LE
MR
V
CC
Pin description
…continued
Pin
11
12
13
14
15
16
Description
latch output
latch output
data input
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
6. Functional description
Table 3.
Function table
[1]
Input
MR
Reset (clear)
L
Demultiplexer
L
(active HIGH 8-channel)
decoder (when D = H)
LE
H
L
D
X
d
d
d
d
d
d
d
d
Memory (no action)
Addressable latch
H
H
H
L
X
d
d
d
d
d
d
d
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Operating mode
Output
A0
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
A1
X
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
A2
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
Q0
L
L
L
L
L
L
L
L
q
0
q
0
q
0
q
0
q
0
q
0
q
0
q
0
Q1
L
Q2
L
L
Q3
L
L
L
Q4
L
L
L
L
Q5
L
L
L
L
L
Q6
L
L
L
L
L
L
Q7
L
L
L
L
L
L
L
Q=d
q
7
q
7
q
7
q
7
q
7
q
7
q
7
Q=d
Q=d L
L
L
L
L
L
L
q
1
Q=d L
L
L
L
L
L
q
2
q
2
Q=d L
L
L
L
L
q
3
q
3
q
3
Q=d L
L
L
L
q
4
q
4
q
4
q
4
Q=d L
L
L
q
5
q
5
q
5
q
5
q
5
Q=d L
L
q
6
q
6
q
6
q
6
q
6
q
6
Q=d L
Q = d q
1
q
1
q
1
q
1
q
1
q
1
q
1
Q = d q
2
q
2
q
2
q
2
q
2
q
2
Q = d q
3
q
3
q
3
q
3
q
3
Q = d q
4
q
4
q
4
q
4
Q = d q
5
q
5
q
5
Q = d q
6
q
6
Q = d q
7
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
4 of 17
NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
Table 4.
LE
L
H
L
H
[1]
Operating mode select table
[1]
MR
H
H
L
L
Mode
addressable latch
memory
active HIGH 8-channel demultiplexer
reset
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP16 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
8. Recommended operating conditions
Table 6.
Symbol
74AHC259
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
74AHCT259
V
CC
V
I
V
O
T
amb
∆t/∆V
74AHC_AHCT259_2
Operating conditions
Parameter
Conditions
Min
2.0
0
0
−40
-
-
4.5
0
0
−40
V
CC
= 4.5 V to 5.5 V
-
Typ
5.0
-
-
+25
-
-
5.0
-
-
+25
-
Max
5.5
5.5
V
CC
+125
100
20
5.5
5.5
V
CC
+125
20
Unit
V
V
V
°C
ns/V
ns/V
V
V
V
°C
ns/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
5 of 17
MCU
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