Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
20-pin SSOP
Junction-to-Ambient Thermal Resistance (θ
JA
) ..........84°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...............32°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
DDL
- V
GNDL
= 1.71V to 5.5V, V
DD
- V
GNDL
= 3.0V to 3.6V, R
ISET
= 120kΩ, T
A
= -40°C to +125°C, V
GNDF
= V
GNDL
. Typical values
are at T
A
= +25°C with V
DDL
= V
DD
= +3.3V, R
ISET
= 120kΩ, V
GNDF
= V
GNDL
.) (Notes 2, 3)
PARAMETER
POWER SUPPLIES
Logic Power Supply
Logic Supply Current
Isolated DC-DC Power
Supply Input Voltage
Isolated DC-DC Supply
Input Current
Logic Power-Up Delay
Field Power-Up Delay
Field Power Supply
Gate Charge Pump
Voltage
Logic-Side Undervoltage
Lockout Threshold
Logic-Side Undervoltage
Lockout Threshold
Hysteresis
Field-Side Undervoltage
Lockout Threshold
V
DDF
V
GATE
V
UVLOL
V
UVLOD
V
UVLHYST
V
UVDHYST
V
UVLOF
(Note 4)
1.95
C
VDDF
= 0.1µF
C
VDDF
= 0.1µF, unregulated output voltage
1µA pull-down
V
DD
≥ 3V
V
DDL
≥ 1.71V
2.5
3
1.5
2.69
3.0
3.6
1.6
2.82
50
100
2.1
2.25
V
DDL
I
DDL
V
DD
I
DD
V
DD
= 3.3V
V
DDL
= 3.3V, no load,
CS
= high
3.0
1.71
0.7
3.3
4.8
5.5
1.5
3.6
8
0.2
1
3.5
4
1.66
2.95
V
mA
V
mA
ms
ms
V
V
V
V
mV
mV
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
www.maximintegrated.com
Maxim Integrated
│
2
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Electrical Characteristics (continued)
(V
DDL
- V
GNDL
= 1.71V to 5.5V, V
DD
- V
GNDL
= 3.0V to 3.6V, R
ISET
= 120kΩ, T
A
= -40°C to +125°C, V
GNDF
= V
GNDL
. Typical values
are at T
A
= +25°C with V
DDL
= V
DD
= +3.3V, R
ISET
= 120kΩ, V
GNDF
= V
GNDL
.) (Notes 2, 3)
PARAMETER
Field-Side Undervoltage
Lockout Threshold
Hysteresis
PROTECTION
ESD
EFT (Burst)
DYNAMIC
Common-Mode Transient
Immunity
ADC AND COMPARATOR
Input Voltage Range
Reference Input Range
ADC Resolution
Gain Error
Offset Error
Differential Nonlinearity
Integral Nonlinearity
Input Leakage Current
Throughput
Latency (No Filtering)
Latency (2 Readings)
Latency (4 Readings)
Latency (8 Readings)
INTERNAL VOLTAGE REFERENCE
Nominal Output Voltage
Output Voltage Accuracy
Output Voltage
Temperature Drift
Reference Voltage
Available Bias Current
When powered from V
DDF
(series) or REFIN
(shunt)
T
CVOUT
Over the entire temperature range
-5
50
1.25
+5
V
%
ppm/°C
AIN step input to COUT transition (Notes 4, 7)
AIN step input to COUT transition (Notes 4, 7)
AIN step input to COUT transition (Notes 4, 7)
AIN step input to COUT transition (Notes 4, 7)
GE
OE
DNL
INL
IILR
Included in the gain + offset window
V
AIN
= 1.25V
-200
8
12
92
180
340
10
V
IN
= 98% V
REF
, excluding offset error and
reference errors
V
IN
= 2% V
REF
, offset calculated
V
AIN
V
REFIN
Nominal measurement range
0
1.15
10
-0.55
-0.2
+0.55
+0.2
±1
±1
+200
12
150
270
510
990
1.25
V
REFIN
(1.25)
1.35
V
V
Bits
%
%FS
LSB
LSB
nA
ksps
µs
µs
µs
µs
CMTI
(Note 6)
50
kV/µs
Any pin to GNDL or GNDF inclusive
System-level requirement IEC 61000-4-4
common mode (Note 5)
±2
3
kV
kV
SYMBOL
V
UVFHYST
CONDITIONS
MIN
TYP
100
MAX
UNITS
mV
EXTERNAL VOLTAGE REFERENCE
1.15
70
1.25
1.35
V
µA
www.maximintegrated.com
Maxim Integrated
│
3
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Electrical Characteristics (continued)
(V
DDL
- V
GNDL
= 1.71V to 5.5V, V
DD
- V
GNDL
= 3.0V to 3.6V, R
ISET
= 120kΩ, T
A
= -40°C to +125°C, V
GNDF
= V
GNDL
. Typical values
are at T
A
= +25°C with V
DDL
= V
DD
= +3.3V, R
ISET
= 120kΩ, V
GNDF
= V
GNDL
.) (Notes 2, 3)
PARAMETER
BIAS CURRENT DAC
Full-Scale Current
Resolution
Offset Error
Integral Nonlinearity
INRUSH CURRENT DAC
Full-Scale Current
Resolution
Offset
Integral Nonlinearity
Inrush Current
INRUSH TIMER
Range
Resolution
Error
DU1 = 0, DU0 = 1 (see INRP register)
Maximum Duty Cycle
Inrush Duration
INRUSH COMPARATOR
Range
Resolution
Latency (No Filtering)
Latency (2 Readings)
Latency (4 Readings)
Latency (8 Readings)
LOGIC I/O LEVELS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
IH
V
IL
V
HYST
SCLK, SDI,
CS
SCLK, SDI,
CS
SCLK, SDI,
CS
0.7 x V
DDL
0.3 x V
DDL
0.05 x
V
DDL
V
V
V
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
From input voltage = INRT until IINR = 50% of set
value (Notes 4, 7)
0
10
22
102
192
356
160
280
520
1000
ADC FS
V
Bits
µs
µs
µs
µs
DU1 = 1, DU0 = 0 (see INRP register)
DU1 = 1, DU0 = 1 (see INRP register)
MAX14002 only
38.4
Nominal
Programmed by TINR[3:0] (see INRP register)
-20
1.6
3.1
6.3
48
57.6
ms
%
0
8
+20
120
ms
ms
%
INL
MAX14002 only. Excludes R
ISET
errors
44.1
IINR[3:0] = 0 (see INRP register)
Excludes R
ISET
errors
94.5
105
7
50
0.25
49
53.9
100
115.5
mA
mA
µA
LSB
mA
INL
IBIAS[3:0] = 0 (see CFG register)
Excludes R
ISET
errors
3.375
3.75
0.25
50
0.25
100
4.125
mA
mA
µA
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
www.maximintegrated.com
Maxim Integrated
│
4
MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Electrical Characteristics (continued)
(V
DDL
- V
GNDL
= 1.71V to 5.5V, V
DD
- V
GNDL
= 3.0V to 3.6V, R
ISET
= 120kΩ, T
A
= -40°C to +125°C, V
GNDF
= V
GNDL
. Typical values
are at T
A
= +25°C with V
DDL
= V
DD
= +3.3V, R
ISET
= 120kΩ, V
GNDF
= V
GNDL
.) (Notes 2, 3)
PARAMETER
Output High Voltage
Output Low Voltage
Output High-Impedance
Leakage Current
Input Leakage Current
Input Capacitance
SCLK Clock Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall-to-SCLK Rise
Time
SCLK Fall-to-CS Rise
Time
SDI Hold Time
SDI Setup Time
SDO Enable Time (CS
Falling to SDO Valid)
SDO Disable Time (CS
Rising to SDO Three-
State)
Output Data Propagation
Delay
Write-Command to Field
Implementation Delay
Inter-Access Gap
SYMBOL
V
OH
V
OL
I
OL
I
IL
C
IN
f
SCLK
t
SCLK
t
SCLKH
t
SCLKL
t
CS(lead)
t
CS(lag)
t
DINH
t
DINSU
t
DOUT(en)
t
DOUT(dis)
t
DO
t
FID
t
IAG
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF. SCLK falling-edge to SDO valid
From
CS
de-assertion until field-side registers
are loaded
Minimum time
CS
must be de-asserted between
commands
920
CONDITIONS
SDO, COUT, sourcing 4mA
SDO, COUT,
FAULT,
sinking 4mA
SDO,
FAULT
SCLK, SDI,
CS
SCLK, SDI,
CS,
f = 1MHz
Single device
Single device
Single device
Single device
200
80
80
80
80
40
40
40
40
50
165
-1
-1
2
5
MIN
V
DDL
- 0.4
0.4
+1
+1
TYP
MAX
UNITS
V
V
µA
µA
pF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPI TIMING CHARACTERISTICS
Note 2:
All devices are 100% production tested at T
A
= +25°C. Specifications for all temperature limits are guaranteed by design.
Note 3:
All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to their
respective ground (GNDL or GNDF), unless otherwise noted.
Note 4:
Guaranteed by characterization; not production tested.
Note 5:
EFT voltage according to IEC 61004-4 is tested through direct coupling to the generator.
Note 6:
CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output states. CMTI
applies to both rising and falling common-mode voltage edges. Tested with the transient generator connected between
GNDF and GNDL (V
CM
= 1000V).
Note 7:
Latency numbers are based on the following condition: a full-scale step is applied at the ADC input and THU is set to mid-scale
value (0x1ff). Latency is the delay from the step at the ADC input to the digital comparator output.
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