NCV5700
High Current IGBT Gate
Driver
The NCV5700 is a high−current, high−performance stand−alone
IGBT driver for high power applications that include solar inverters,
motor control and uninterruptable power supplies. The device offers a
cost−effective solution by eliminating many external components.
Device protection features include Active Miller Clamp, accurate
UVLO, EN input, DESAT protection and Active Low FAULT output.
The driver also features an accurate 5.0 V output and separate high and
low (VOH and VOL) driver outputs for system design convenience.
The driver is designed to accommodate a wide voltage range of bias
supplies including unipolar and bipolar voltages. It is available in a
16−pin SOIC package.
Features
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MARKING
DIAGRAM
NCV5700DR2G
AWLYWW
SOIC−16
D SUFFIX
CASE 751B
A
WL
Y
WW
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages
Low Output Impedance of VOH & VOL for Enhanced IGBT Driving
Short Propagation Delays with Accurate Matching
Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer
for Isolated Drive, Logic Compatibility for Non−isolated Drive
Active Miller Clamp to Prevent Spurious Gate Turn−on
DESAT Protection with Programmable Delay
Enable Input for Independent Driver Control
Tight UVLO Thresholds for Bias Flexibility
Wide Bias Voltage Range including Negative VEE Capability
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable, Grade 1
This Device is Pb−Free, Halogen−Free and RoHS Compliant
Motor Control
Uninterruptible Power Supplies (UPS)
Automotive Power Supplies
HEV/EV Powertrain
HEV/EV PTC Heaters
VREF
DESAT
VCC
EN
VOH
VOL
CLAMP
GND
VEE
VCC
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
EN
VIN
VREF
FLT
GNDA
NC
RSVD
NC
1
2
3
4
5
6
7
8
(Top View)
16 CLAMP
15 VEEA
14 VEE
13 GND
12 VOL
11 VOH
10 VCC
9
DESAT
Typical Applications
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
VIN
VEE
FLT
Figure 1. Simplified Application Schematic
©
Semiconductor Components Industries, LLC, 2017
1
September, 2017 − Rev. 0
Publication Order Number:
NCV5700/D
NCV5700
TSD
Q
SET
S
Q
CLR
R
FLT
I
DESAT-CHG
DESAT
V
DESAT-THR
+
-
S
SET
V
REF
DELAY
Q
R
EN-H
EN
V
CC
R
CLR
Q
V
REF
R
IN-H
V
IN
Bandgap
DELAY
V
OH
V
OL
V
EE
-
+
S
SET
V
REF
V
CC
V
UVLO
Q
R
CLR
Q
-
+
V
MC-THR
CLAMP
GND
V
EE
Figure 2. Detailed Block Diagram
VREF
V
EEA
EN
VREF
CLAMP
CLAMP
VIN
VCC
VREF
VEEA
LDO
Logic Unit
VEE
FLT
GND
GNDA
VOL
NC
VOH
TSD
RSVD
VCC
VCC
UVLO
NC
DESAT
Figure 3. Simplified Block Diagram
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DESAT
NCV5700
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
EN
VIN
No.
1
2
I/O/x
I
I
Description
Enable input allows additional gating of VOH and VOL, and can be used when the driver output
needs to be turned off independent of the Microcontroller input.
Input signal to control the output. In applications which require galvanic isolation, VIN is generated
at the opto output, the pulse transformer secondary or the digital isolator output. There is a signal
inversion from VIN to VOH/VOL. VIN is internally clamped to 5.5 V and has a pull−up resistor of
1 MW to ensure that output is low in the absence of an input signal. A minimum pulse−width is re-
quired at VIN before VOH/VOL are activated.
5 V Reference generated within the driver is brought out to this pin for external bypassing and for
powering low bias circuits (such as digital isolators).
Fault output (active low) that allows communication to the main controller that the driver has en-
countered a fault condition and has deactivated the output. Truth Table is provided in the datasheet
to indicate conditions under which this signal is asserted. Capable of driving optos or digital isolators
when isolation is required.
This pin provides a convenient connection point for bypass capacitors (e.g REF) on the left side of
the package.
Pins not internally connected.
Reserved. No connection is allowed.
Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to this
pin allows a programmable blanking delay every ON cycle before DESAT fault is processed, thus
preventing false triggering.
Positive bias supply for the driver. The operating range for this pin is from UVLO to the maximum. A
good quality bypassing capacitor is required from this pin to GND and should be placed close to the
pins for best results.
Driver high output that provides the appropriate drive voltage and source current to the IGBT gate.
Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate. VOL
is actively pulled low during start−up and under Fault conditions.
This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.
A negative voltage with respect to GND can be applied to this pin and that will allow VOL to go to a
negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to GND.
If a negative voltage is not applied or available, this pin must be connected to GND.
Analog version of the VEE pin for any signal trace connection. VEE and VEEA are internally con-
nected.
Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To be
tied directly to IGBT gate with minimum trace length for best results.
VREF
FLT
3
4
O
O
GNDA
NC
RSVD
DESAT
5
6,8
7
9
x
x
x
I
VCC
10
x
VOH
VOL
GND
VEE
11
12
13
14
O
O
x
x
VEEA
CLAMP
15
16
x
I/O
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NCV5700
Table 2. ABSOLUTE MAXIMUM RATINGS
(Note 1)
Parameter
Differential Power Supply
Positive Power Supply
Negative Power Supply
Gate Output High
Gate Output Low
Input Voltage
Enable Voltage
DESAT Voltage
FLT Current
Sink
Source
Power Dissipation
SO−16 package
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Moisture Sensitivity Level
Lead Temperature Soldering Reflow
(SMD Styles Only), Pb−Free Versions (Note 3)
Symbol
V
CC
−V
EE
(V
max
)
V
CC
−GND
V
EE
−GND
V
OH
−GND
V
OL
−GND
V
IN
−GND
V
EN
−GND
V
DESAT
−GND
I
FLT−SINK
I
FLT−SRC
PD
900
T
J(max)
TSTG
ESDHBM
ESDMM
MSL
T
SLD
150
−65 to 150
4
200
1
260
°C
°C
kV
V
−
°C
V
EE
− 0.3
−0.3
−0.3
−0.3
5.5
5.5
V
CC
+ 0.3
20
25
mW
Minimum
0
−0.3
−18
Maximum
36
22
0.3
V
CC
+ 0.3
Unit
V
V
V
V
V
V
V
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating:
≤
100 mA per JEDEC standard: JESD78, 125°C
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 3. THERMAL CHARACTERISTICS
Parameter
Thermal Characteristics, SOIC−16 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Symbol
R
θJA
Value
145
Unit
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm
2
(or 0.16 in
2
) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. OPERATING RANGES
(Note 6)
Parameter
Differential Power Supply
Positive Power Supply
Negative Power Supply
Input Voltage
Enable Voltage
Input Pulse Width
Ambient Temperature
Symbol
V
CC
−V
EE
(V
max
)
V
CC
V
EE
V
IN
V
EN
t
on
T
A
UVLO
−15
0
0
40
−40
125
Min
Max
30
20
0
5
5
Unit
V
V
V
V
V
ns
°C
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCV5700
Table 5. ELECTRICAL CHARACTERISTICS
V
CC
= 15 V, V
EE
= 0 V, Kelvin GND connected to V
EE
. For typical values T
A
= 25°C,
for min/max values, T
A
is the operating ambient temperature range that applies, unless otherwise noted.
Parameter
LOGIC INPUT and OUTPUT
Input Threshold Voltages
High−state (Logic 1) Required
Low−state (Logic 0) Required
No state change
Enable Threshold Voltages
High−state
Low−state
Input/Enable Internal Pull−Up
Resistance to VREF
Input/Enable Current
High−state
Low−state
Input Pulse−Width
No Response at the Output
Guaranteed Response at the
Output
FLT Threshold Voltage
Low State
High State
DRIVE OUTPUT
Output Low State
I
sink
= 200 mA, T
A
= 25°C
I
sink
= 200 mA, T
A
= −40°C to 125°C
I
sink
= 1.0 A, T
A
= 25°C
Output High State
I
src
= 200 mA, T
A
= 25°C
I
src
= 200 mA, T
A
= −40°C to 125°C
I
src
= 1.0 A, T
A
= 25°C
Peak Driver Current, Sink
(Note 7)
R
G
= 0.1
W,
V
CC
= 15 V, V
EE
= −8 V
V
O
= 13 V
V
O
= 9 V (near Miller Plateau)
R
G
= 0.1
W,
V
CC
= 15 V, V
EE
= −8 V
V
O
= −5 V
V
O
= 9 V (near Miller Plateau)
V
OH1
V
OH2
V
OH3
I
PK−snk1
I
PK−snk2
I
PK−src1
I
PK−src2
14.5
14.2
13.8
14.8
14.7
14.1
A
6.8
6.1
A
7.8
4.0
V
OL1
V
OL2
V
OL3
0.1
0.2
0.8
0.2
0.5
1.2
V
V
V
IN−H
/V
EN−H
= 4.5 V
V
IN−L
/V
EN−L
= 0.5 V
Voltage thresholds consistent with input
specs
Pulse−Width = 150 ns, V
EN
= 5 V
Voltage applied to get output to go low
Voltage applied to get output to go high
Voltage applied without change in output state
V
IN
= 0 V
Voltage applied to get output to go high
Voltage applied to get output to go low
V
V
IN−H1
V
IN−L1
V
IN−NC
V
EN−H
V
EN−L
R
IN−H
/
R
EN−H
I
IN−H
/I
EN−H
I
IN−L
/I
EN−L
t
on−min1
t
on−min2
4.3
1.2
4.3
0.75
1
MW
mA
1
10
ns
10
30
V
(I
FLT−SINK
= 15 mA)
(I
FLT−SRC
= 20 mA)
V
FLT−L
V
FLT−H
12
0.5
13.9
1.0
0.75
3.7
V
Test Conditions
Symbol
Min
Typ
Max
Unit
Peak Driver Current, Source
(Note 7)
DYNAMIC CHARACTERISTICS
Turn−on Delay
(see timing diagram)
Turn−off Delay
(see timing diagram)
Propagation Delay Distortion
(=t
pd−on
− t
pd−off
)
Prop Delay Distortion between
Parts (Note 7)
Rise Time (Note 7)
(see timing diagram)
Fall Time (Note 7)
(see timing diagram)
C
load
= 1.0 nF
C
load
= 1.0 nF
Negative input pulse width = 10
ms
Positive input pulse width = 10
ms
For input or output pulse width > 150 ns,
T
A
= 25°C
T
A
= −40°C to 125°C
t
pd−on
t
pd−off
45
45
56
63
75
75
ns
ns
ns
t
distort1
t
distort2
t
distort −tot
t
rise
t
fall
−15
−25
−30
−7
0
9.2
7.9
5
25
30
ns
ns
ns
7. Values based on design and/or characterization.
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