SID11x1K
SCALE-iDriver
Family
Up to 8 A Single Channel IGBT/MOSFET Gate Driver Providing
Reinforced Galvanic Isolation up to 650 V Blocking Voltage
Product Highlights
Highly Integrated, Compact Footprint
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Description
The SID11x1K is a single channel IGBT and MOSFET driver in an
eSOP package. Reinforced galvanic isolation is provided by Power
Integrations’ innovative solid insulator FluxLink technology. 8 A peak
output drive current enables the product to drive devices up to 600 A
(typical) without requiring any additional active components. For gate
drive requirements that exceed the stand-alone capability of the
SID11x1K’s, an external amplifier (booster) may be added. Stable
positive and negative voltages for gate control are provided by one
unipolar isolated voltage source.
Additional features such as short-circuit protection (DESAT) with
Advanced Soft Shut Down (ASSD), undervoltage lock-out (UVLO) for
primary-side and secondary-side and rail-to-rail output with tempera-
ture and process compensated output impedance guarantee safe
operation even in harsh conditions.
Controller (PWM and fault) signals are compatible with 5 V CMOS logic,
which may also be adjusted to 15 V levels by using external resistor divider.
Split outputs providing up to 8 A peak drive current
Integrated FluxLink™ technology
Rail-to-rail stabilized output voltage
Unipolar supply voltage for secondary-side
Suitable for 600 V / 650 V / 1200 V IGBT and MOSFET switches
Providing basic isolation up to 1200 V blocking voltage
Up to 75 kHz switching frequency
Low propagation delay time 260 ns
Propagation delay jitter ±5 ns
-40 °C to 125 °C operating ambient temperature
High common-mode transient immunity
eSOP package with 9.5 mm creepage and clearance
Advanced Protection / Safety Features
•
Undervoltage lock-out (UVLO) protection for primary and
secondary-side and fault feedback
•
Short-circuit protection using V
CESAT
monitoring and fault feedback
•
Advanced Soft Shut Down (ASSD)
Full Safety and Regulatory Compliance
Product Portfolio
Product
1
SID1151K
SID1181K
Table 1. SCALE-iDriver Portfolio.
Notes:
1. Package: eSOP-R16B.
•
100% production partial discharge test
•
100% production HIPOT compliance testing at 6 kV RMS 1 s
•
Reinforced insulation meets VDE 0884-10
Peak Output Drive Current
5.0 A
8.0 A
Green Package
Applications
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Halogen free and RoHS compliant
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Delivery vehicles
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General purpose drives
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General industrial equipment
Figure 2.
SCALE-iDriver
VCE
eSOP-R16B Package.
Primary-Side
Logic
Secondary-Side
Logic
VGXX
IN
Fault
Output
V
IN
VISO
SO
GH
VCC
V
TOT
+
-
V
VCC
+
-
GND
FluxLink
GL
VEE
COM
Figure 1.
www.power.com
Typical Application Schematic.
PI-7949-072616
May 2018
This Product is Covered by Patents and/or Pending Patent Applications.
SID11x1K
+
VCE
V
DES
VGXX
SHORT-CIRCUIT
DETECTION
VCC
ASSD
BOOTSTRAP
CHARGE PUMP
COM
VISO
LEVEL
SHIFTER
GH
SO
TRANSCEIVER
(BIDIRECTIONAL)
FluxLink
TRANSCEIVER
(BIDIRECTIONAL)
VISO
GL
CORE LOGIC
SUPPLY
MONITORING
AUXILIARY
POWER SUPPLIES
VISO
VEE CONTROL
VEE
GND
IN
CORE LOGIC
SUPPLY
MONITORING
AUXILIARY
POWER SUPPLIES
COM
PI-7654-092216
Figure 3.
Functional Block Diagram.
Pin Functional Description
VCC Pin (Pin 1):
This pin is the primary-side supply voltage connection.
GND Pin (Pin 3-6):
This pin is the connection for the primary-side ground potential.
All primary-side voltages refer to the pin.
IN Pin (Pin 7):
This pin is the input for the logic command signal.
SO Pin (Pin 8):
This pin is the output for the logic fault signal (open drain).
NC Pin (Pin 9):
This pin must be un-connected. Minimum PCB pad size for soldering
is required.
VEE Pin (Pin 10):
Common (IGBT emitter/MOSFET source) output supply voltage.
VCE Pin (Pin 11):
This pin is the desaturation monitoring voltage input connection.
VGXX Pin (Pin 12):
This pin is the bootstrap and charge pump supply voltage source.
GH Pin (Pin 13):
This pin is the driver output – sourcing current (turn-on) connection.
VISO Pin (Pin 14):
This pin is the input for the secondary-side positive supply voltage.
COM Pin (Pin 15):
This pin provides the secondary-side reference potential.
GL Pin (Pin 16):
This pin is the driver output – sinking current (turn-off).
VCC 1
GND 3-6
IN 7
SO 8
16 GL
15 COM
14 VISO
13 GH
12 VGXX
11 VCE
10 VEE
9 NC
PI-7648-041415
Figure 4.
Pin Configuration.
2
Rev. B 05/18
www.power.com
SID11x1K
SCALE-iDriver Functional Description
The single channel SCALE-iDriver
™
family is designed to drive IGBTs
and MOSFETs or other semiconductor power switches with a blocking
voltage of up to 1200 V and provide reinforced isolation between
micro-controller and the power semiconductor switch. The logic
input (PWM) command signals applied via the IN pin and the primary
supply voltage supplied via the VCC pin are both referenced to the
GND pin. The working status of the power semiconductor switch and
SCALE-iDriver is monitored via the SO pin.
PMW command signals are transferred from the primary (IN) to
secondary-side via FluxLink isolation technology. The GH pin supplies
a positive gate voltage and charges the semiconductor gate during
the turn-on process. The GL pin supplies the negative voltage and
discharges the gate during the turn-off process.
Short-circuit protection is implemented using a desaturation detection
technique monitored via the VCE pin. When the SCALE-iDriver detects
a short-circuit, the semiconductor turn-off process is activated
using an Advanced Soft Shut Down (ASSD) technique.
Power Supplies
The SID11x1K requires two power supplies. One is the primary-side
(V
VCC
) which powers the primary-side logic and communication with
the secondary (insulated) side. Another supply voltage is required for
the secondary-side, V
TOT
is applied between the VISO pin and the
COM pin. V
TOT
needs to be insulated from the primary-side and must
provide at least the same insulation capabilities as the SCALE-iDriver.
V
TOT
must have a low capacitive coupling to the primary or any other
secondary-side. The positive gate-emitter voltage V
VISO
is provided by
VISO which is internally generated and stabilized to 15 V (typically)
with respect to VEE. The negative gate-emitter voltage V
VEE
is
provided by VEE with respect to COM. Due to the limited current
sourcing capabilities of the VEE pin, any additional load needs to be
applied between the VISO and COM pins. No additional load between
VISO and VEE pins or between VEE and COM pins is allowed.
Input and Fault Logic (Primary-Side)
The input (IN) and output (SO) logic is designed to work directly with
micro-controllers using 5 V CMOS logic. If the physical distance
between the controller and the SCALE-iDriver is large or if a different
logic level is required the resistive divider in Figure 5, or Schmitt-trigger
ICs (Figures 13 and 14) can be used. Both solutions adjust the logic level
as necessary and will also improve the driver’s noise immunity.
Gate driver commands are transferred from the IN pin to the GH and
GL pins with a propagation delay t
P(LH)
and t
P(HL)
.
During normal operation, when there is no fault detected, the SO pin
stays at high impedance (open). Any fault is reported by connecting
the SO pin to GND. The SO pin stays low as long as the V
VCC
voltage
(primary-side) stays below UVLO
VCC
, where the propagation delay is
negligible. If desaturation is detected (there is a short-circuit), or the
supply voltages V
VISO
, V
VEE
, (secondary-side) drop below UVLO
VISO
,
UVLO
VEE
, the SO status changes with a delay time t
FAULT
and keeps
status low for a time defined as t
SO
. In case of a fault condition the
driver applies the off-state (the GL pin is connected to COM). During
the t
SO
period, command signal transitions from the IN pin are
ignored. A new turn-on command transition is required before the
driver will enter the on-state.
The SO pin current is defined as I
SO
; voltage during low status is
defined as V
SO(FAULT)
.
Output (Secondary-Side)
The gate of the power semiconductor switch to be driven can be
connected to the SCALE-iDriver output via pins GH and GL, using two
different resistor values. Turn-on gate resistor R
GON
needs to be
SCALE-iDriver
R
1
R
2
R
SO
C
1
GND
IN
SO
VCC
PI-7950-050916
Figure 5.
Increased Threshold Voltages V
IN+LT
and V
IN+HT
. For R
1
= 3.3 kW and
R
2
= 1 kW the IN Logic Level is 15 V.
connected to the GH pin and turn-off gate resistor R
GOFF
to the GL pin.
If both gate resistors have the same value, the GL and GH pins can be
connected together. Note: The SCALE-iDriver data sheet defines the
R
GH
and R
GL
values as total resistances connected to the respective
pins GH and GL. Note that most power semiconductor data sheets
specify an internal gate resistor R
GINT
which is already integrated into
the power semiconductor switch. In Addition to R
GINT
, external
resistor devices R
GON
and R
GOFF
are specified to setup the gate current
levels to the application requirements. Consequently, R
GH
is the sum
of R
GON
and R
GINT
, as shown in Figures 9 and 10. Careful consideration
should be given to the power dissipation and peak current associated
with the external gate resistors.
The GH pin output current source (I
GH
) of SID1181K is capable of
handling up to 7.3 A during turn-on, and the GL pin output current
source (I
GL
) is able to sink up to 8.0 A during turn-off. The SCALE-
iDriver’s internal resistances are described as R
GHI
and R
GLI
respec-
tively. If the gate resistors for SCALE-iDriver family attempt to draw
a higher peak current, the peak current will be internally limited to a
safe value, see Figures 6 and 7. Figure 8 shows the peak current
PI-7910-121516
9
Turn-On Peak Gate Current I
GH
(A)
8
7
6
5
4
3
2
1
0
R
GH
= 4
Ω,
R
GL
= 3.4
Ω,
C
LOAD
= 47 nF
R
GH
= 4
Ω,
R
GL
= 3.4
Ω,
C
LOAD
= 100 nF
R
GH
= R
GL
= 0
Ω,
C
LOAD
= 47 nF
-60
-40
-20
0
20
40
60
80
100
120
140
Ambient Temperature (°C)
Figure 6.
Turn-On Peak Output Current (Source) vs. Ambient Temperature.
Conditions: V
CC
= 5 V, V
TOT
= 25 V, f
S
= 20 kHz, Duty Cycle = 50%.
3
www.power.com
Rev. B 05/18
SID11x1K
PI-7911-042816
PI-7912-042816
0
7
6
Turn-Off Peak Gate Current I
GL
(A)
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
Gate Peak Current (A)
R
GH
= 4
Ω,
R
GL
= 3.4
Ω,
C
LOAD
= 47 nF
R
GH
= 4
Ω,
R
GL
= 3.4
Ω,
C
LOAD
= 100 nF
R
GH
= R
GL
= 0
Ω,
C
LOAD
= 47 nF
5
4
3
2
1
0
I
GH
, Turn-On Peak Gate Current
I
GL
, Turn-Off Peak Gate Current
-60
-40
-20
0
20
40
60
80
100
120
140
20
21
22
23
24
25
26
27
28
29
30
Ambient Temperature (°C)
Figure 7.
Turn-Off Peak Output Current (Sink) vs. Ambient Temperature.
Conditions: V
VCC
= 5 V, V
TOT
= 25 V, f
S
= 20 kHz, Duty Cycle = 50%
Figure 8.
Secondary-Side Total Supply Voltage – V
TOT
(V)
Turn-On and Turn-Off Peak Output Current vs. Secondary-Side Total
Supply Voltage (V
TOT
). Conditions: V
VCC
= 5 V, T
J
= 25 °C, R
GH
= 4
W,
R
GL
= 3.4
W,
C
LOAD
= 100 nF, f
S
= 1 kHz, Duty Cycle = 50%.
that can be achieved for a given supply voltage for same gate resistor
values, load capacitance and layout design.
Short-Circuit Protection
The SCALE-iDriver uses the semiconductor desaturation effect to
detect short-circuits and protects the device against damage by
employing an Advanced Soft Shut Down (ASSD) technique. Desatu-
ration can be detected using two different circuits, either with diode
sense circuitry D
VCE
(Figure 10) or with resistors R
VCEX
(Figure 9). With
the help of a well stabilized V
VISO
and a Schottky diode (D
STO
) connected
between semiconductor gate and VISO pin the short-circuit current
value can be limited to a safe value.
During the off-state, the VCE pin is internally connected to the COM
pin and C
RES
is discharged (red curve in Figure 11 represents the
potential of the VCE pin). When the power semiconductor switch
receives a turn-on command, the collector-emitter voltage (V
CE
)
decreases from the off-state level same as the DC-link voltage to a
normally much lower on-state level (see blue curve in Figure 11) and
C
RES
begins to be charged up to the V
CE
saturation level (V
CE SAT
). C
RES
charging time depends on the resistance of R
VCEX
(Figure 9), DC-link
voltage and C
RES
and R
VCE
value. The V
CE
voltage during on-state is
continuously observed and compared with a reference voltage, V
DES
.
The V
DES
level is optimized for IGBT applications. As soon as V
CE
>V
DES
(red circle in Figure 11), the driver turns off the power semiconductor
switch with a controlled collector current slope, limiting the V
CE
overvoltage excursions to below the maximum collector-emitter
voltage (V
CES
). Turn-on commands during this time and during t
SO
are
ignored, and the SO pin is connected to GND.
The response time t
RES
is the C
RES
charging time and describes the
delay between V
CE
asserting and the voltage on the VCE pin rising
(see Figure 11). Response time should be long enough to avoid false
tripping during semiconductor turn-on and is adjustable via R
RES
and
C
RES
(Figure 10) or R
VCE
and C
RES
(Figure 9) values. It should not be
longer than the period allowed by the semiconductor manufacturer.
Safe Power-Up and Power-Down
During driver power-up and power-down, several unintended input /
output states may occur. In order to avoid these effects, it is
recommended that the IN pin is kept at logic low during power-up
SCALE-iDriver
VCE
R
VCE
R
VCEX
VGXX
C
RES
C
GXX
D
CL
VISO
GH
R
GON
R
GOFF
D
STO
Collector
Gate R
GINT
GL
Emitter
VEE
COM
PI-7952-080416
Figure 9.
Short-Circuit Protection using a Resistor Chain R
VCEX
.
and power-down. Any supply voltage related to VCC, VISO, VEE and
VGXX pins should be stabilized using ceramic capacitors C
1
, C
S1X
, C
S2X
,
C
GXX
respectively as shown in Figures 13 and 14. After supply
voltages reach their nominal values, the driver will begin to function
after a time delay t
START
.
Short-Pulse Operation
If command signals applied to the IN pin are shorter than the minimum
specified by t
GE(MIN)
, the SCALE-iDriver output signals, GH and GL pins,
will be extended to value t
GE(MIN)
. The duration of pulses longer than
t
GE(MIN)
will not be changed.
4
Rev. B 05/18
www.power.com
SID11x1K
SCALE-iDriver
VCE
V
R
VCE
D
VCE
VGXX
C
RES
C
GXX
R
RES
V
CE
(IGBT) Signal
Fault
VISO
V
DES
R
GON
R
GOFF
D
STO
Collector
GH
V
CE SAT
t
RES
t
Gate R
GINT
GL
Emitter
VEE
VCE Pin Signal
COM
COM
PI-7951-080416
PI-7671-093016
Figure 10. Short-Circuit Protection Using Rectifier Diode D
VCE
.
Figure 11. Short-Circuit Protection Using Resistors Chain R
VCEX
.
Advanced Soft Shut Down (ASSD)
This function is activated when a short-circuit is detected. It protects
the power semiconductor switch against destruction by ending the
turn-on state and limiting the current slope in order to keep momen-
tary V
CE
overvoltages below V
CES
. This function is particularly suited to
IGBT applications. Figure 12 shows how the ASSD function operates.
The V
CE
desaturation is visible during time period P1 (yellow line).
During this time, the gate-emitter voltage (green line) is kept very
stable. Collector current (pink line) is also well stabilized and limited
to a safe value. At the end of period P1, V
GE
is reduced during t
FSSD1
.
Due to collector current decrease a small V
CE
overvoltage is seen.
During t
FSSD1
V
GE
is further reduced and the gate of the power
semiconductor switch is further discharged. During t
FSSD2
additional
small V
CE
overvoltage events may occur. Once V
GE
drops below the
gate threshold of the IGBT, the collector current has decayed almost to
zero and the remaining gate charge is removed ‒ ending the short-
circuit event. The whole short-circuit current detection and safe
switch-off is lower than 10
µs
(8
µs
in this example).
V
GE
t
FSSD1
I
GE
V
CE
I
CE
t
FSSD2
P1
Figure 12. Advanced Soft Shut Down Function.
5
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Rev. B 05/18
Microcontroller MCU
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