VN7140AS12
High-side driver with Multisense analog feedback for automotive
applications
Datasheet - production data
Features
Max transient supply voltage
Operating voltage range
Typ. on-state resistance (per
Ch)
Minimum cranking supply
voltage
(V
CC
decreasing)
Current limitation (typ.)
Standby current (max.)
V
CC
V
CC
R
ON
40 V
4 to
28 V
140 mΩ
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Loss of ground and V
CC
Reverse battery with external
components
Electrostatic discharge protection
Applications
All types of automotive resistive, inductive
and capacitive loads
Specially intended for automotive signal
lamps (up to R10W or LED Rear
Combinations)
V
USD_Cranking
I
LIMH
I
STBY
2.85 V
12 A
0.5 µA
Description
The device is single channel high-side driver
manufactured using ST proprietary VIPower
®
M0-7 technology and housed in the SO-8
package. It is designed to drive 12 V automotive
grounded loads through a 3 V and 5 V CMOS-
compatible interface, and to provide protection
and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown.
A dedicated Multisense pin delivers high
precision proportional load current sense, in
addition to the detection of overload and short
circuit to ground, short to V
CC
and OFF-state
open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
AEC-Q100 qualified
Extreme low voltage operation for deep cold
cranking applications (compliant with LV124,
revision 2013)
General
Single channel smart high-side driver
with Multisense analog feedback
Very low standby current
Compatible with 3 V and 5 V CMOS
outputs
Multisense diagnostic functions
Analog feedback of load current with
high precision proportional current
mirror
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open-load detection
Output short to V
CC
detection
Sense enable/disable
February 2018
DocID029756 Rev 2
1/39
www.st.com
This is information on a product in full production.
Contents
VN7140AS12
Contents
1
2
Block diagram and pin description ................................................ 5
Electrical specification .................................................................... 7
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings ................................................................ 7
Thermal data ..................................................................................... 8
Main electrical characteristics ........................................................... 8
Waveforms ...................................................................................... 17
Electrical characteristics curves ...................................................... 17
Power limitation ............................................................................... 21
Thermal shutdown ........................................................................... 21
Current limitation ............................................................................. 21
Negative voltage clamp ................................................................... 21
GND protection network against reverse battery............................. 22
4.1.1
Diode (DGND) in the ground line ..................................................... 23
3
Protections..................................................................................... 21
3.1
3.2
3.3
3.4
4
Application information ................................................................ 22
4.1
4.2
4.3
4.4
Immunity against transient electrical disturbances .......................... 23
MCU I/Os protection ........................................................................ 24
Multisense - analog current sense .................................................. 24
4.4.1
4.4.2
Principle of Multisense signal generation ......................................... 25
Short to VCC and OFF-state open-load detection ........................... 28
5
6
7
Maximum demagnetization energy (VCC = 16 V) ........................ 29
Package and PCB thermal data .................................................... 30
6.1
7.1
7.2
7.3
SO-8 thermal data ........................................................................... 30
SO-8 package information .............................................................. 33
SO-8 packing information ................................................................ 34
SO-8 marking information ............................................................... 36
Package information ..................................................................... 33
8
9
Order code ..................................................................................... 37
Revision history ............................................................................ 38
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DocID029756 Rev 2
VN7140AS12
List of tables
List of tables
Table 1: Pin functions ................................................................................................................................. 5
Table 2: Suggested connections for unused and not connected pins ........................................................ 6
Table 3: Absolute maximum ratings ........................................................................................................... 7
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Electrical characteristics during cranking ..................................................................................... 8
Table 6: Power section ............................................................................................................................... 9
Table 7: Switching..................................................................................................................................... 10
Table 8: Logic inputs ................................................................................................................................. 10
Table 9: Protections .................................................................................................................................. 11
Table 10: Multisense ................................................................................................................................. 11
Table 11: Truth table ................................................................................................................................. 16
Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 23
Table 13: Multisense pin levels in off-state ............................................................................................... 27
Table 14: PCB properties ......................................................................................................................... 30
Table 15: Thermal parameters ................................................................................................................. 32
Table 16: SO-8 mechanical data .............................................................................................................. 33
Table 17: Reel dimensions ....................................................................................................................... 34
Table 18: SO-8 carrier tape dimensions ................................................................................................... 35
Table 19: Device summary ....................................................................................................................... 37
Table 20: Document revision history ........................................................................................................ 38
DocID029756 Rev 2
3/39
List of figures
VN7140AS12
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE versus IOUT ....................................................................................................... 14
Figure 5: Current sense accuracy versus IOUT ....................................................................................... 14
Figure 6: Switching time and pulse skew.................................................................................................. 15
Figure 7: Multisense timings (current sense mode) .................................................................................. 15
Figure 8: TDSTKON.................................................................................................................................. 16
Figure 9: Standby mode activation ........................................................................................................... 17
Figure 10: Standby state diagram ............................................................................................................. 17
Figure 11: OFF-state output current ......................................................................................................... 17
Figure 12: Standby current ....................................................................................................................... 17
Figure 13: IGND(ON) vs. Tcase ............................................................................................................... 18
Figure 14: Logic input high level voltage .................................................................................................. 18
Figure 15: Logic input low level voltage .................................................................................................... 18
Figure 16: High level logic input current ................................................................................................... 18
Figure 17: Low level logic input current .................................................................................................... 18
Figure 18: Logic input hysteresis voltage ................................................................................................. 18
Figure 19: On-state resistance vs. Tcase ................................................................................................. 19
Figure 20: On-state resistance vs. VCC ................................................................................................... 19
Figure 21: Turn-on voltage slope .............................................................................................................. 19
Figure 22: Turn-off voltage slope .............................................................................................................. 19
Figure 23: Won vs. Tcase ......................................................................................................................... 19
Figure 24: Woff vs. Tcase ......................................................................................................................... 19
Figure 25: ILIMH vs. Tcase ....................................................................................................................... 20
Figure 26: OFF-state open-load voltage detection threshold ................................................................... 20
Figure 27: Vsense clamp vs. Tcase.......................................................................................................... 20
Figure 28: Vsenseh vs. Tcase .................................................................................................................. 20
Figure 29: Undervoltage shutdown ........................................................................................................... 20
Figure 30: Application diagram ................................................................................................................. 22
Figure 31: Simplified internal structure ..................................................................................................... 22
Figure 32: Multisense and diagnostic – block diagram ............................................................................. 24
Figure 33: Multisense block diagram ........................................................................................................ 25
Figure 34: Analogue HSD – open-load detection in off-state ................................................................... 26
Figure 35: Open-load / short to VCC condition ......................................................................................... 27
Figure 36: Maximum turn off current versus inductance .......................................................................... 29
Figure 37: S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) ........................................................... 30
Figure 38: SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) .......................................................... 30
Figure 39: SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) ........... 31
Figure 40: SO-8 thermal impedance junction ambient single pulse (one channel on) ............................. 31
Figure 41: Thermal fitting model of a double-channel HSD in SO-8 ........................................................ 32
Figure 42: SO-8 package outline .............................................................................................................. 33
Figure 43: Reel for SO-8 ........................................................................................................................... 34
Figure 44: SO-8 carrier tape ..................................................................................................................... 35
Figure 45: SO-8 schematic drawing of leader and trailer tape ................................................................. 36
Figure 46: SO-8 marking information........................................................................................................ 36
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DocID029756 Rev 2
VN7140AS12
Block diagram and pin description
1
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Name
V
CC
OUTPUT
GND
INPUT
Multisense
SEn
Battery connection.
Power outputs.
Ground connection. Must be reverse battery protected by an external diode / resistor
network.
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS
outputs. It controls output switch state.
Multiplexed analog sense output pin; it delivers a current proportional to the load
current.
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the Multisense
diagnostic pin.
Function
DocID029756 Rev 2
5/39
PCB Design
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