1Gb: x4, x8, x16 DDR3L SDRAM
Description
DDR3L SDRAM
MT41K256M4 – 32 Meg x 4 x 8 banks
MT41K128M8 – 16 Meg x 8 x 8 banks
MT41K64M16 – 8 Meg x 16 x 8 banks
Description
The 1.35V DDR3L SDRAM device is a low-voltage ver-
sion of the 1.5V DDR3 SDRAM device. Refer to the
DDR3 (1.5V) SDRAM data sheet specifications when
running in 1.5V compatible mode.
• Write leveling
• Multipurpose register
• Output driver calibration
Options
1
• Configuration
– 256 Meg x 4
– 128 Meg x 8
– 64 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball FBGA (8mm x 11.5mm) Rev.
G
– 78-ball FBGA (8mm x 10.5mm) Rev. J
• FBGA package (Pb-free) – x16
– 96-ball FBGA (8mm x 14mm) Rev. G
– 96-ball FBGA (8mm x 14mm) Rev. J
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
– Industrial (–40°C
≤
T
C
≤
+95°C)
• Revision
Note:
Marking
256M4
128M8
64M16
JP
DA
JT
TW
-107
-125
-15E
-187E
None
IT
:G / :J
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= +1.35V (1.283V to 1.45V)
Backward compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-107
1, 2, 3
-125
1, 2
-15E
1
187E
Notes:
Data Rate (MT/s)
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
PDF: CCMTD-1725822587-774
1Gb_DDR3L.pdf - Rev. L EN 9/18
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
Page Size
256 Meg x 4
32 Meg x 4 x 8 banks
8K
16K A[13:0]
8 BA[2:0]
2K A[11, 9:0]
1KB
128 Meg x 8
16 Meg x 8 x 8 banks
8K
16K A[13:0]
8 BA[2:0]
1K A[9:0]
1KB
64 Meg x 16
8 Meg x 16 x 8 banks
8K
8K A[12:0]
8 BA[2:0]
1K A[9:0]
2KB
Figure 1: DDR3 Part Numbers
Example Part Number: MT41K256M4DA-125:J
-
MT41K
Configuration
Package
Speed
:
Revision
{
:G / :J Revision
Temperature
256M4
128M8
64M16
Rev.
G
G
J
J
Mark
JP
JT
DA
TW
-107
-125
-15E
-187E
Speed Grade
tCK = 1.07ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 7
Commercial
Industrial temperature
None
IT
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
Package
78-ball 8mm x 11.5mm FBGA
96-ball 8mm x 14mm FBGA
78-ball 8mm x 10.5mm FBGA
96-ball 8mm x 14mm FBGA
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
PDF: CCMTD-1725822587-774
1Gb_DDR3L.pdf - Rev. L EN 9/18
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Description
Contents
Important Notes and Warnings ....................................................................................................................... 11
State Diagram ................................................................................................................................................ 12
Functional Description ................................................................................................................................... 13
Industrial Temperature ............................................................................................................................... 13
General Notes ............................................................................................................................................ 13
Functional Block Diagrams ............................................................................................................................. 15
Ball Assignments and Descriptions ................................................................................................................. 17
Package Dimensions ....................................................................................................................................... 23
Electrical Specifications .................................................................................................................................. 27
Absolute Ratings ......................................................................................................................................... 27
Input/Output Capacitance .......................................................................................................................... 28
Thermal Characteristics .................................................................................................................................. 29
Electrical Specifications – I
DD
Specifications and Conditions ............................................................................ 31
Electrical Characteristics – I
DD
Specifications .................................................................................................. 42
Electrical Specifications – DC and AC .............................................................................................................. 46
DC Operating Conditions ........................................................................................................................... 46
Input Operating Conditions ........................................................................................................................ 47
DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 51
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 55
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 57
ODT Characteristics ....................................................................................................................................... 58
1.35V ODT Resistors ................................................................................................................................... 59
ODT Sensitivity .......................................................................................................................................... 60
ODT Timing Definitions ............................................................................................................................. 60
Output Driver Impedance ............................................................................................................................... 64
34 Ohm Output Driver Impedance .............................................................................................................. 65
DDR3L 34 Ohm Driver ................................................................................................................................ 66
DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 67
DDR3L Alternative 40 Ohm Driver ............................................................................................................... 68
DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 68
Output Characteristics and Operating Conditions ............................................................................................ 70
Reference Output Load ............................................................................................................................... 73
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 73
Slew Rate Definitions for Differential Output Signals .................................................................................... 75
Speed Bin Tables ............................................................................................................................................ 76
Electrical Characteristics and AC Operating Conditions ................................................................................... 80
Command and Address Setup, Hold, and Derating ........................................................................................... 98
Data Setup, Hold, and Derating ...................................................................................................................... 105
Commands – Truth Tables ............................................................................................................................. 114
Commands ................................................................................................................................................... 117
DESELECT ................................................................................................................................................ 117
NO OPERATION ........................................................................................................................................ 117
ZQ CALIBRATION LONG ........................................................................................................................... 117
ZQ CALIBRATION SHORT .......................................................................................................................... 117
ACTIVATE ................................................................................................................................................. 117
READ ........................................................................................................................................................ 117
WRITE ...................................................................................................................................................... 118
PRECHARGE ............................................................................................................................................. 119
REFRESH .................................................................................................................................................. 119
SELF REFRESH .......................................................................................................................................... 120
PDF: CCMTD-1725822587-774
1Gb_DDR3L.pdf - Rev. L EN 9/18
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Description
DLL Disable Mode ..................................................................................................................................... 121
Input Clock Frequency Change ...................................................................................................................... 125
Write Leveling ............................................................................................................................................... 127
Write Leveling Procedure ........................................................................................................................... 129
Write Leveling Mode Exit Procedure ........................................................................................................... 131
Initialization ................................................................................................................................................. 132
Voltage Initialization/Change ........................................................................................................................ 134
V
DD
Voltage Switching ............................................................................................................................... 135
Mode Registers .............................................................................................................................................. 136
Mode Register 0 (MR0) ................................................................................................................................... 137
Burst Length ............................................................................................................................................. 137
Burst Type ................................................................................................................................................. 138
DLL RESET ................................................................................................................................................ 139
Write Recovery .......................................................................................................................................... 140
Precharge Power-Down (Precharge PD) ...................................................................................................... 140
CAS Latency (CL) ....................................................................................................................................... 140
Mode Register 1 (MR1) ................................................................................................................................... 142
DLL Enable/DLL Disable ........................................................................................................................... 142
Output Drive Strength ............................................................................................................................... 143
OUTPUT ENABLE/DISABLE ...................................................................................................................... 143
TDQS Enable ............................................................................................................................................. 143
On-Die Termination .................................................................................................................................. 144
WRITE LEVELING ..................................................................................................................................... 144
POSTED CAS ADDITIVE Latency ................................................................................................................ 144
Mode Register 2 (MR2) ................................................................................................................................... 145
CAS Write Latency (CWL) ........................................................................................................................... 146
AUTO SELF REFRESH (ASR) ....................................................................................................................... 146
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 147
SRT vs. ASR ............................................................................................................................................... 147
DYNAMIC ODT ......................................................................................................................................... 147
Mode Register 3 (MR3) ................................................................................................................................... 148
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 148
MPR Functional Description ...................................................................................................................... 149
MPR Register Address Definitions and Bursting Order ................................................................................. 150
MPR Read Predefined Pattern .................................................................................................................... 156
MODE REGISTER SET (MRS) Command ........................................................................................................ 156
ZQ CALIBRATION Operation ......................................................................................................................... 157
ACTIVATE Operation ..................................................................................................................................... 158
READ Operation ............................................................................................................................................ 160
WRITE Operation .......................................................................................................................................... 171
DQ Input Timing ....................................................................................................................................... 179
PRECHARGE Operation ................................................................................................................................. 181
SELF REFRESH Operation .............................................................................................................................. 181
Extended Temperature Usage ........................................................................................................................ 183
Power-Down Mode ........................................................................................................................................ 184
RESET Operation ........................................................................................................................................... 192
On-Die Termination (ODT) ............................................................................................................................ 194
Functional Representation of ODT ............................................................................................................. 194
Nominal ODT ............................................................................................................................................ 194
Dynamic ODT ............................................................................................................................................... 196
Dynamic ODT Special Use Case ................................................................................................................. 196
Functional Description .............................................................................................................................. 196
PDF: CCMTD-1725822587-774
1Gb_DDR3L.pdf - Rev. L EN 9/18
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Description
Synchronous ODT Mode ................................................................................................................................ 202
ODT Latency and Posted ODT .................................................................................................................... 202
Timing Parameters .................................................................................................................................... 202
ODT Off During READs .............................................................................................................................. 205
Asynchronous ODT Mode .............................................................................................................................. 207
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 209
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 211
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 213
PDF: CCMTD-1725822587-774
1Gb_DDR3L.pdf - Rev. L EN 9/18
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
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