All other packages, excluding SFN .............................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching Threshold
Input Low Voltage
Low-to-High Switching Threshold
Switching Hysteresis
Output Low Voltage
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
(Notes 2, 3)
(Notes 2, 4)
(Notes 5, 6)
IO at V
PUPMAX
(Notes 6, 7, 8)
(Notes 2, 9)
(Notes 6, 7, 10)
(Notes 6, 7, 11)
At 4mA (Note 12)
Standard speed
Overdrive speed
Recovery Time
(Notes 2, 13)
t
REC
V
PUP
+4.5V
640µs
Directly prior to reset pulse
Standard speed
Time-Slot Duration
(Notes 2, 14)
t
SLOT
Standard speed, V
PUP
Overdrive speed
+4.5V
+4.5V
5
2
1
5
10
65
61
8
7
480
480
48
15
2
60
8
60
6
960
640
80
60
6
240
24
75
10
µs
µs
µs
µs
µs
µs
1.0
0.2
0.05
0.5
2.8
0.3
2000
5
V
PUP
-
1.8
0.5
V
PUP
-
1.0
1.7
0.4
5.25
2.2
V
k
pF
µA
V
V
V
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Directly prior to reset pulse
>
640µs
Overdrive speed, V
PUP
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time
(Note 2)
Presence-Detect High Time
Presence-Detect Low Time
Presence-Detect Sample Time
(Notes 2, 15)
2
Standard speed, t
REC
before reset = 10µs
t
RSTL
Standard speed, t
REC
before reset = 5µs
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
t
PDH
t
PDL
t
MSP
Maxim Integrated
DS24B33
1-Wire 4Kb EEPROM
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 16)
Write-One Low Time
(Notes 2, 16)
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 17)
Read Sample Time
(Notes 2, 17)
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (Endurance)
(Notes 20, 21)
Data Retention (Notes 22, 23, 24)
I
PROG
t
PROG
N
CY
t
DR
(Note 18)
(Note 19)
At +25°C
At +85°C (worst case)
At +85°C (worst case)
200,000
50,000
40
2
5
mA
ms
—
Years
t
RL
t
MSR
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
1
t
RL
+
t
RL
+
15 -
2-
15
2
µs
µs
t
W0L
t
W1L
Standard speed
Overdrive speed
Standard speed
Overdrive speed
60
6
5
1
120
16
15
2
µs
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
System requirement.
When operating near the minimum operating voltage (2.8V), a falling edge slew rate of 15V/µs or faster is recommended.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times,
and current requirements during EEPROM programming. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found
in the DS2482-x00 or DS2480B may be required.
Capacitance on the data pin could be 2500pF when V
PUP
is first applied. Once the parasite capacitance is charged, it
does not affect normal communication.
Guaranteed by design, characterization, and/or simulation only. Not production tested.
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of
V
TL
, V
TH
, and V
HY
.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to V
ILMAX
at all times while the master is driving IO to a logic 0 level.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
The I-V characteristic is linear for voltages less than +1V.
Applies to a single DS24B33 attached to a 1-Wire line.
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS24B33 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
ε
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε,
respectively.
δ
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO should be such that during the
programming interval, the voltage at IO is greater than or equal to V
PUPMIN
. If V
PUP
in the system is close to V
PUPMIN
, then
a low-impedance bypass of R
PUP
, which can be activated during programming, may need to be added.
Maxim Integrated
3
DS24B33
1-Wire 4Kb EEPROM
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
Note 19:
The t
PROG
interval begins after the trailing rising edge on IO for the last time slot of the E/S byte for a valid copy scratch-
pad sequence. The interval ends once the device’s self-timed EEPROM programming cycle is complete and the current
drawn by the device has returned from I
PROG
to I
L
.
Note 20:
Write-cycle endurance is degraded as T
A
increases.
Note 21:
Not 100% production tested; guaranteed by reliability monitor sampling.
Note 22:
Data retention is degraded as T
A
increases.
Note 23:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
Note 24:
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
Pin Configurations
SIDE VIEW
TOP VIEW
GND
1
2
3
1
2
3
FRONT VIEW
+
N.C.
1
8
N.C.
IO
N.C.
N.C.
2
DS24B33
7
N.C.
TO-92
FRONT VIEW (T&R VERSION)
1
IO
3
6
N.C.
GND
4
5
N.C.
2
SO
(208 mils)
3
TOP VIEW
DS24B33
6
24B33
ymrrF
N.C.
BOTTOM VIEW
1
2
+
N.C.
1
IO
2
5
N.C.
DS24B33
IO
GND
GND
3
*EP
4
N.C.
SFN
(6mm
×
6mm
×
0.9mm)
TDFN
(3mm
×
3mm)
*EXPOSED PAD
NOTE:
THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT
APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, REFER TO
APPLICATION NOTE 4132: ATTACHMENT METHODS FOR ELECTRO-MECHANICAL
SFN PACKAGE.
4
Maxim Integrated
DS24B33
1-Wire 4Kb EEPROM
Pin Description
PIN
SFN
2
1
—
—
TDFN-EP
3
2
1, 4, 5, 6
—
TO-92
1
2
3
—
SO
4
3
1, 2, 5–8
—
NAME
GND
IO
N.C.
EP
Ground Reference
1-Wire Bus Interface. Open-drain pin that requires external pullup
Not Connected
Exposed Pad (TDFN only). Solder evenly to the board’s ground plane for
proper operation. Refer to Application Note 3273:
Exposed Pads: A Brief
Introduction
for additional information.
FUNCTION
Detailed Description
The DS24B33 combines 4Kb of data EEPROM with a
fully featured 1-Wire interface in a single chip. The
memory is organized as 16 pages of 256 bits each. A
volatile 256-bit memory page called the scratchpad
acts as a buffer when writing data to the EEPROM to
ensure data integrity. Data is first written to the scratch-
pad, from which it can be read back for verification
before transferring it to the EEPROM. The operation of
the DS24B33 is controlled over the single-conductor
1-Wire bus. Device communication follows the standard
1-Wire protocol. The energy required to read and write
the DS24B33 is derived entirely from the 1-Wire com-
munication line. Each DS24B33 has its own unalterable
and unique 64-bit registration number. The registration
number guarantees unique identification and is used to
address the device in a multidrop 1-Wire net environ-
ment. Multiple DS24B33 devices can reside on a com-
mon 1-Wire bus and be operated independently of
each other. Applications of the DS24B33 include cali-
bration data storage, PCB identification, and storage of
product revision status. The DS24B33 provides a high
degree of backward compatibility with the DS2433,
including having the same family code.
Overview
Figure 1 shows the relationships between the major
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Embedded System
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