1.125Gb: x18, x36 RLDRAM 3
Features
RLDRAM 3
MT44K64M18 – 4 Meg x 18 x 16 Banks
MT44K32M36 – 2 Meg x 36 x 16 Banks
Features
• 1200 MHz DDR operation (2400 Mb/s/ball data
rate)
• 86.4Gb/s peak bandwidth (x36 at 1200 MHz clock
frequency)
• Organization
– 64 Meg x 18, and 32 Meg x 36 common I/O (CIO)
– 16 banks
• 1.2V center-terminated push/pull I/O
• 2.5V V
EXT
, 1.35V V
DD
, 1.2V V
DDQ
(optional 1.35V
V
DDQ
for 2400 operation only).
• Reduced cycle time (
t
RC (MIN) = 6.67 - 8ns)
• SDR addressing
• Programmable READ/WRITE latency (RL/WL) and
burst length
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Free-running differential input data clocks (DKx,
DKx#) and output data clocks (QKx, QKx#)
• On-die DLL generates CK edge-aligned data and
differential output data clock signals
• 64ms refresh (128K refresh per 64ms)
• 168-ball BGA package
•
Ω
or 60Ω matched impedance outputs
• Integrated on-die termination (ODT)
• Single or multibank writes
• Extended operating range (200–1200 MHz)
• READ training register
• Multiplexed and non-multiplexed addressing capa-
bilities
• Mirror function
• Output driver and ODT calibration
• JTAG interface (IEEE 1149.1-2001)
Options
1
• Clock cycle and
t
RC timing
– 0.83ns and
t
RC (MIN) = 6.67ns
(RL3-2400)
– 0.83ns and
t
RC (MIN) = 7.5ns
(RL3-2400)
– 0.93ns and
t
RC (MIN) = 7.5ns
(RL3-2133)
– 0.93ns and
t
RC (MIN) = 8ns
(RL3-2133)
– 1.07ns and
t
RC (MIN) = 8ns
(RL3-1866)
• Configuration
– 64 Meg x 18
– 32 Meg x 36
• Operating temperature
– Commercial (T
C
= 0° to +95°C)
– Industrial (T
C
= –40°C to +95°C)
• Package
– 168-ball BGA (Pb-free)
• Revision
Note:
Marking
-083F
-083E
-093F
-093E
-107E
64M18
32M36
None
IT
RB
:A
1. Not all options listed can be combined to
define an offered product. Use the part cat-
alog search on
www.micron.com
for availa-
ble offerings.
PDF: 09005aef85a88362
1.125Gb_rldram3.pdf – Rev. D 08/16 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1.125Gb: x18, x36 RLDRAM 3
Features
Figure 1: 1Gb RLDRAM
®
3 Part Numbers
Example Part Number: MT44K32M36RB-093E:A
-
MT44K
Configuration Package
Speed Temp
:
Rev
Revision
Configuration
64 Meg x 18
32 Meg x 36
64M18
32M36
Die Rev
Temperature
Commercial
Industrial
Package
168-ball BGA (Pb-free)
RB
Speed Grade
-083F
t
CK = 0.83ns (6.67ns
t
RC)
-083E
t
CK = 0.83ns (7.5ns
t
RC)
-093F
t
CK = 0.93ns (7.5ns
t
RC)
-093E
t
CK = 0.93ns (8ns
t
RC)
-107E
t
CK = 1.07ns (8ns
t
RC)
None
IT
:A
BGA Part Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s BGA Part Marking Decoder is available on Micron’s Web site at
www.micron.com.
PDF: 09005aef85a88362
1.125Gb_rldram3.pdf – Rev. D 08/16 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 RLDRAM 3
Features
Contents
General Description ......................................................................................................................................... 9
General Notes .............................................................................................................................................. 9
State Diagram ................................................................................................................................................ 10
Functional Block Diagrams ............................................................................................................................. 11
Ball Assignments and Descriptions ................................................................................................................. 13
Package Dimensions ....................................................................................................................................... 17
Electrical Characteristics – I
DD
Specifications .................................................................................................. 18
Electrical Specifications – Absolute Ratings and I/O Capacitance ..................................................................... 22
Absolute Maximum Ratings ........................................................................................................................ 22
Input/Output Capacitance .......................................................................................................................... 22
AC and DC Operating Conditions .................................................................................................................... 23
AC Overshoot/Undershoot Specifications .................................................................................................... 25
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 28
Slew Rate Definitions for Differential Input Signals ...................................................................................... 30
ODT Characteristics ....................................................................................................................................... 31
ODT Resistors ............................................................................................................................................ 31
ODT Sensitivity .......................................................................................................................................... 33
Output Driver Impedance ............................................................................................................................... 33
Output Driver Sensitivity ............................................................................................................................ 34
Output Characteristics and Operating Conditions ............................................................................................ 36
Reference Output Load ............................................................................................................................... 39
Slew Rate Definitions for Single-Ended Output Signals ..................................................................................... 40
Slew Rate Definitions for Differential Output Signals ........................................................................................ 41
Speed Bin Tables ............................................................................................................................................ 42
AC Electrical Characteristics ........................................................................................................................... 43
Temperature and Thermal Impedance Characteristics ..................................................................................... 49
Command and Address Setup, Hold, and Derating ........................................................................................... 51
Data Setup, Hold, and Derating ....................................................................................................................... 58
Commands .................................................................................................................................................... 65
MODE REGISTER SET (MRS) Command ......................................................................................................... 66
Mode Register 0 (MR0) .................................................................................................................................... 67
t
RC ............................................................................................................................................................. 68
Data Latency .............................................................................................................................................. 68
DLL Enable/Disable ................................................................................................................................... 68
Address Multiplexing .................................................................................................................................. 68
Mode Register 1 (MR1) .................................................................................................................................... 70
Output Drive Impedance ............................................................................................................................ 70
DQ On-Die Termination (ODT) ................................................................................................................... 70
DLL Reset ................................................................................................................................................... 70
ZQ Calibration ............................................................................................................................................ 71
ZQ Calibration Long ................................................................................................................................... 72
ZQ Calibration Short ................................................................................................................................... 72
AUTO REFRESH Protocol ............................................................................................................................ 73
Burst Length (BL) ....................................................................................................................................... 73
Mode Register 2 (MR2) .................................................................................................................................... 75
READ Training Register (RTR) ..................................................................................................................... 75
WRITE Protocol .......................................................................................................................................... 78
Post Package Repair – PPR .............................................................................................................................. 78
PPR Row Repair Sequence .......................................................................................................................... 78
WRITE Command .......................................................................................................................................... 80
PDF: 09005aef85a88362
1.125Gb_rldram3.pdf – Rev. D 08/16 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 RLDRAM 3
Features
Multibank WRITE ....................................................................................................................................... 80
READ Command ............................................................................................................................................ 81
AUTO REFRESH Command ............................................................................................................................ 83
INITIALIZATION Operation ............................................................................................................................ 85
WRITE Operation ........................................................................................................................................... 87
READ Operation ............................................................................................................................................. 91
AUTO REFRESH Operation ............................................................................................................................. 94
RESET Operation ............................................................................................................................................ 97
Clock Stop ...................................................................................................................................................... 98
Mirror Function ............................................................................................................................................. 99
Multiplexed Address Mode ............................................................................................................................. 100
Data Latency in Multiplexed Address Mode ................................................................................................ 105
REFRESH Command in Multiplexed Address Mode .................................................................................... 105
IEEE 1149.1 Serial Boundary Scan (JTAG) ....................................................................................................... 109
Disabling the JTAG Feature ........................................................................................................................ 109
Test Access Port (TAP) ................................................................................................................................ 109
TAP Controller ........................................................................................................................................... 110
Performing a TAP RESET ............................................................................................................................ 112
TAP Registers ............................................................................................................................................ 112
TAP Instruction Set .................................................................................................................................... 113
PDF: 09005aef85a88362
1.125Gb_rldram3.pdf – Rev. D 08/16 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 RLDRAM 3
Features
Figure 1: 1Gb RLDRAM
®
3 Part Numbers ......................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 10
Figure 3: 64 Meg x 18 Functional Block Diagram ............................................................................................. 11
Figure 4: 32 Meg x 36 Functional Block Diagram ............................................................................................. 12
Figure 5: 168-Ball BGA ................................................................................................................................... 17
Figure 6: Single-Ended Input Signal ............................................................................................................... 24
Figure 7: Overshoot ....................................................................................................................................... 25
Figure 8: Undershoot .................................................................................................................................... 25
Figure 9: V
IX
for Differential Signals ................................................................................................................ 26
Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 27
Figure 11: Definition of Differential AC Swing and
t
DVAC ................................................................................ 27
Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 29
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 30
Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 31
Figure 15: Output Driver ................................................................................................................................ 34
Figure 16: DQ Output Signal .......................................................................................................................... 38
Figure 17: Differential Output Signal .............................................................................................................. 39
Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 39
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 40
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 41
Figure 21: Example Temperature Test Point Location ...................................................................................... 50
Figure 22: Nominal Slew Rate and
t
VAC for
t
IS (Command and Address – Clock) .............................................. 54
Figure 23: Nominal Slew Rate for
t
IH (Command and Address – Clock) ............................................................ 55
Figure 24: Tangent Line for
t
IS (Command and Address – Clock) ..................................................................... 56
Figure 25: Tangent Line for
t
IH (Command and Address – Clock) ..................................................................... 57
Figure 26: Nominal Slew Rate and
t
VAC for
t
DS (DQ – Strobe) .......................................................................... 61
Figure 27: Nominal Slew Rate for
t
DH (DQ – Strobe) ....................................................................................... 62
Figure 28: Tangent Line for
t
DS (DQ – Strobe) ................................................................................................. 63
Figure 29: Tangent Line for
t
DH (DQ – Strobe) ................................................................................................ 64
Figure 30: MRS Command Protocol ............................................................................................................... 66
Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 67
Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 70
Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 72
Figure 34: Read Burst Lengths ........................................................................................................................ 74
Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 75
Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 77
Figure 37: Entry, Repair, and Exit Timing Diagram .......................................................................................... 79
Figure 38: WRITE Command ......................................................................................................................... 80
Figure 39: READ Command ........................................................................................................................... 82
Figure 40: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 83
Figure 41: Multibank AUTO REFRESH Command ........................................................................................... 84
Figure 42: Power-Up/Initialization Sequence ................................................................................................. 86
Figure 43: WRITE Burst ................................................................................................................................. 87
Figure 44: Consecutive WRITE Bursts ............................................................................................................. 88
Figure 45: WRITE-to-READ ............................................................................................................................ 88
Figure 46: WRITE - DM Operation .................................................................................................................. 89
Figure 47: Consecutive Quad Bank WRITE Bursts ........................................................................................... 89
Figure 48: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 90
Figure 49: Basic READ Burst .......................................................................................................................... 91
Figure 50: Consecutive READ Bursts (BL = 2) .................................................................................................. 92
List of Figures
PDF: 09005aef85a88362
1.125Gb_rldram3.pdf – Rev. D 08/16 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
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