8Gb: 2 Channels x16/x8 GDDR6 SGRAM Networking
Features
GDDR6 SGRAM for Networking
MT61M256M32
2 Channels x 256 Meg x 16 I/O, 2 Channels x 512 Meg x 8 I/O
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= 1.25V ±3%
V
PP
= 1.8V –3%/+6%
Data rate: 10 Gb/s, 12 Gb/s
2 separate independent channels (x16)
x16/x8 and 2-channel/pseudo channel (PC) mode
configurations set at reset
Single ended interfaces per channel for command/
address (CA) and data
Differential clock input CK_t/CK_c for CA per 2
channels
One differential clock input WCK_t/WCK_c per
channel for data (DQ, DBI_n, EDC)
Double data rate (DDR) command/address (CK)
Quad data rate (QDR) and double data rate (DDR)
data (WCK), depending on operating frequency
16n prefetch architecture with 256 bits per array
read or write access
16 internal banks
4 bank groups for
t
CCDL = 3
t
CK and 4
t
CK
Programmable READ latency
Programmable WRITE latency
Write data mask function via CA bus with single and
double byte mask granularity
Data bus inversion (DBI) and CA bus inversion
(CABI)
Input/output PLL
CA bus training: CA input monitoring via DQ/
DBI_n/EDC signals
WCK2CK clock training with phase information via
EDC signals
Data read and write training via read FIFO (depth =
6)
Read/write data transmission integrity secured by
cyclic redundancy check using half data rate CRC
Programmable CRC READ latency
Programmable CRC WRITE latency
Programmable EDC hold pattern for CDR
RDQS mode on EDC pins
Low power modes
• On‐chip temperature sensor with read‐out
• Auto precharge option for each burst access
• Auto refresh mode (32ms, 16k cycles) with per-bank
and per-2-bank refresh options
• Temperature sensor controlled self refresh rate
• Digital
t
RAS lockout
• On‐die termination (ODT) for all high‐speed inputs
• Pseudo open drain (POD125) compatible outputs
• ODT and output driver strength auto calibration
with external resistor ZQ pin (120Ω)
• Internal V
REF
with DFE for data inputs, with input
receiver characteristics programmable per pin
• Selectable external or internal V
REF
for CA inputs;
programmable V
REF
offsets for internal V
REF
• Vendor ID for device identification
• IEEE 1149.1 compliant boundary scan
• 180-ball BGA package
• Lead-free (RoHS-compliant) and halogen-free
packaging
• T
C
= 0°C to +95°C (Commercial) and –40°C to +95°C
(Industrial)
Options
1
• Organization
– 256 Meg × 32 (words × bits)
• FBGA package
– 180-ball (12.0mm × 14.0mm)
• Timing – maximum data rate
– 10 Gb/s
– 12 Gb/s
• Application code
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
– Industrial (–40°C
≤
T
C
≤
+95°C)
• Revision
Note:
Marking
256M32
JE
-10
-12
N
None
IT
A
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
CCMTD-1412786195-10193
gddr6_sgram_8gb_brief_networking.pdf - Rev. G 8/18 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM Networking
Features
Figure 1: Part Numbering
MT 61 M 256M32 JE -10 N IT : A
Micron Memory
Product Family
61 = GDDR6 SGRAM
Operating Voltage
M = 1.25V
Configuration
256M32 = 256 Meg x 32
Package
JE = 180-ball FBGA, 12.0mm x 14.0mm
Revision A
Temperature
IT = Industrial
Blank = Commercial
Application Code
N = Networking
Data Rate
-10 = 10 Gb/s
-12 = 12 Gb/s
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s web site:
http://www.micron.com.
CCMTD-1412786195-10193
gddr6_sgram_8gb_brief_networking.pdf - Rev. G 8/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM Networking
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 2: 180-Ball FBGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
DD
V
SS
V
DDQ
V
SS
V
DD Q
V
SS
V
SS
V
DDQ
RESET _n
V
REFC
V
DDQ
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
2
V
SS
DQ3_A
EDC0_A
DBI0_n_A
DQ5_A
DQ6_A
DQ7_A
V
DD
V
DDQ
V
DDQ
V
DD
DQ7_B
DQ6_B
DQ5_B
DBI0_n_B
EDC0_B
DQ3_B
V
SS
3
DQ1_A
DQ2_A
V
SS
V
SS
DQ4_A
V
SS
V
SS
CA0_A
CA9_A
CA9_B
CA0_B
V
SS
V
SS
DQ4_B
V
SS
V
SS
DQ2_B
DQ1_B
4
V
SS
DQ0_A
V
DDQ
WCK_t
_A
V
SS
V
DDQ
CA2_A
V
SS
CA8_A
CA8_B
V
SS
CA2_B
V
DDQ
V
SS
NC
V
DDQ
DQ0_B
V
SS
5
V
PP
V
DDQ
V
SS
WCK_c
_A
V
DD
TMS
NC
CA4_A
CABI_n_A
CABI_n_B
CA4_B
NC
TCK
V
DD
NC
V
SS
V
DDQ
V
PP
6
7
8
9
10
V
PP
V
DDQ
V
SS
NC
V
DD
TDI
CKE_n_A
CA5_A
CK_t
C K _c
CA5_B
CKE_n_B
TDO
V
DD
WCK_c
_B
V
SS
V
DDQ
V
PP
11
V
SS
DQ8_A
V
DDQ
NC
V
SS
V
DDQ
CA1_A
V
SS
CA7_A
CA7_B
V
SS
CA1_B
V
DDQ
V
SS
WCK_t
_B
V
DDQ
DQ8_B
V
SS
12
DQ9_A
DQ10_A
V
SS
V
SS
DQ12_A
V
SS
V
SS
CA3_A
CA6_A
CA6_B
CA3_B
V
SS
V
SS
DQ12_B
V
SS
V
SS
DQ10_B
DQ9_B
13
V
SS
DQ11_A
EDC1_A
DBI1_n_A
DQ13_A
DQ14_A
DQ15_A
V
DD
V
DDQ
V
DDQ
V
DD
DQ15_B
DQ14_B
DQ13_B
DBI1_n_B
EDC1_B
DQ11_B
V
SS
14
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
V
DDQ
ZQ_A
ZQ_B
V
DDQ
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Data
Command/
Address
Other signal
Supply
Ground
Note:
1. Channel A byte 1 and channel B byte 0 are disabled when the device is configured to x8
mode.
CCMTD-1412786195-10193
gddr6_sgram_8gb_brief_networking.pdf - Rev. G 8/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM Networking
Ball Assignments and Descriptions
Table 1: 180-Ball FBGA Ball Descriptions
Symbol
CK_t,
CK_c
Type
Input
Description
Clock:
CK_t and CK_c are differential clock inputs. CK_t and CK_c do not have chan-
nel indicators as one clock is shared between both channel A and channel B on a de-
vice. Command address (CA) inputs are latched on the rising and falling edge of CK.
All latencies are referenced to CK.
Write clock:
WCK_t and WCK_c are differential clocks used for write data capture
and read data output. WCK_t/WCK_c are associated with DQ[15:0], DBI[1:0]_n, and
EDC[1:0].
Clock enable:
CKE_n LOW activates and CKE_n HIGH deactivates the internal clock,
device input buffers, and output drivers excluding RESET_n, TDI, TDO, TMS, and TCK.
Taking CKE_n HIGH provides PRECHARGE POWER-DOWN and SELF REFRESH opera-
tions (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE_n
must be maintained LOW throughout read and write accesses.
Command address (CA):
The CA inputs receive packetized DDR command, address
or other information, for example, the op-code for the MRS command. See Com-
mand Truth Table for details.
Command address bus inversion
Data input/output:
Bidirectional 16-bit data bus.
Data bus inversion:
DBI0_n is associated with DQ[7:0], DBI1_n is associated with
DQ[15:8].
Error detection code:
The calculated CRC data is transmitted on these signals. In
addition these signals drive a "hold" pattern when idle. EDC0 is associated with
DQ[7:0], EDC1 is associated with DQ[15:8].
I/O power supply:
Isolated on the die for improved noise immunity.
Power supply
Ground
Pump voltage
Reference voltage for CA, CABI_n, and CKE_n signals
External reference for auto calibration
JTAG test data input
JTAG test data output
JTAG test mode select
JTAG test clock
Reset:
RESET_n low asynchronously initiates a full chip reset. With RESET_n LOW all
ODTs are disabled. A full chip reset may be performed at any time by pulling RE-
SET_n LOW.
No connect
1. Index "_A" or "_B" represents the channel indicator "A" and "B" of the device. Signal
names including the channel indicator are used whenever more than one channel is ref-
erenced, for example, with the ball assignment. The channel indicator is omitted when-
ever features and functions common to both channels are described.
WCK_t,
WCK_c
CKE_n
Input
Input
CA[9:0]
Input
CABI_n
DQ[15:0]
DBI[1:0]_n
EDC[1:0]
Input
I/O
I/O
Output
V
DDQ
V
DD
V
SS
V
PP
V
REFC
ZQ
TDI
TDO
TMS
TCK
RESET_n
Supply
Supply
Supply
Supply
Supply
Reference
Input
Output
Input
Input
Input
NC
Note:
–
CCMTD-1412786195-10193
gddr6_sgram_8gb_brief_networking.pdf - Rev. G 8/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM Networking
Package Dimensions
Package Dimensions
Figure 3: 180-Ball FBGA (JE)
0.12
Seating plane
A
0.1 A
0.6 CTR
nonconductive
overmold
180X Ø0.47
Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.
Ball A1 ID
(covered by SR)
14 13 12 11 10
5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Ball A1 ID
14 ±0.1
12.75 CTR
0.75 TYP
0.75 TYP
9.75 CTR
12 ±0.1
1.1 ±0.1
0.34 ±0.05
Notes:
1. Package dimension specification is compliant to JC11 MO328 variation P14.0x12.0-
GJ-180A.
2. All dimensions are in millimeters.
3. Solder ball material: SAC-Q (92.5% Sn, 4% Ag, 3% Bi, 0.5% Cu).
CCMTD-1412786195-10193
gddr6_sgram_8gb_brief_networking.pdf - Rev. G 8/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
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