MT48LC8M16A2P-6A:L TR datasheet, PDF

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MT48LC8M16A2P-6A:L TR: DescriptionDynamic Random Access Memory S Dynamic Random Access Memory 128M 8MX16 TSOP; Categorysemiconductor Memory IC Dynamic random access memory; File Size1MB，87 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT48LC8M16A2P-6A:L TR Overview

Dynamic Random Access Memory S Dynamic Random Access Memory 128M 8MX16 TSOP

MT48LC8M16A2P-6A:L TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	SDRAM
Data bus width	16 bit
organize	8 M x 16
Package/box	TSOP-54
storage	128 Mbit
maximum clock frequency	167 MHz
interview time	17 ns
Supply voltage - max.	3.6 V
Supply voltage - min.	3 V
Supply current—max.	100 mA
Minimum operating temperature	0 C
Maximum operating temperature	+ 70 C
series	MT48LC
Encapsulation	Cut Tape
Encapsulation	MouseReel
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	2000

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128Mb: x4, x8, x16 SDRAM

Features

SDR SDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 Banks

MT48LC16M8A2 – 4 Meg x 8 x 4 Banks

MT48LC8M16A2 – 2 Meg x 16 x 4 Banks

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths (BL): 1, 2, 4, 8, or full

page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh modes: Standard and low power

(not available on AT devices)

• Auto Refresh

– 64ms, 4096-cycle refresh (commercial and

industrial)

– 16ms, 4096-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

Options

• Plastic package – OCPL

– 54-pin TSOP II (400 mil)

– 54-pin TSOP II (400 mil) Pb-free

– 60-ball TFBGA (8mm x 16mm)

– 60-ball TFBGA (8mm x 16mm) Pb-

free

– 54-ball VFBGA (x16 only) (8mm x

8mm)

– 54-ball VFBGA (x16 only) (8mm x

8mm) Pb-free

• Timing – cycle time

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

– 6.0ns @ CL = 3 (x16 only)

• Self refresh

– Standard

– Low power

• Revision

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

Notes:

1. Contact Micron for availability.

2. Off-center parting line.

3. Only available on Revision G.

Marking

-75

-7E

-6A

None

:G/:L

None

Options

• Configurations

– 32 Meg x 4 (8 Meg x 4 x 4 banks)

– 16 Meg x 8 (4 Meg x 8 x 4 banks)

– 8 Meg x 16 (2 Meg x 16 x 4 banks)

• Write recovery (

WR)

–

WR = 2 CLK

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-6A

-75

-7E

Clock

Frequency (MHz)

167

133

Marking

32M4

16M8

8M16

Target

RCD-

RP-CL

3-3-3

2-2-2

RCD

(ns)

CL (ns)

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

128Mb: x4, x8, x16 SDRAM

Features

Contents

Important Notes and Warnings ......................................................................................................................... 7

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 8

Functional Block Diagrams ............................................................................................................................... 9

Pin and Ball Assignments and Descriptions ..................................................................................................... 12

Package Dimensions ....................................................................................................................................... 16

Temperature and Thermal Impedance ............................................................................................................ 19

Electrical Specifications .................................................................................................................................. 23

Electrical Specifications – I

Parameters ........................................................................................................ 25

Electrical Specifications – AC Operating Conditions ......................................................................................... 27

Functional Description ................................................................................................................................... 30

Commands .................................................................................................................................................... 31

COMMAND INHIBIT .................................................................................................................................. 31

NO OPERATION (NOP) ............................................................................................................................... 32

LOAD MODE REGISTER (LMR) ................................................................................................................... 32

ACTIVE ...................................................................................................................................................... 32

READ ......................................................................................................................................................... 33

WRITE ....................................................................................................................................................... 34

PRECHARGE .............................................................................................................................................. 35

BURST TERMINATE ................................................................................................................................... 35

REFRESH ................................................................................................................................................... 36

AUTO REFRESH ..................................................................................................................................... 36

SELF REFRESH ....................................................................................................................................... 36

Truth Tables ................................................................................................................................................... 37

Initialization .................................................................................................................................................. 42

Mode Register ................................................................................................................................................ 44

Burst Length .............................................................................................................................................. 46

Burst Type .................................................................................................................................................. 46

CAS Latency ............................................................................................................................................... 48

Operating Mode ......................................................................................................................................... 48

Write Burst Mode ....................................................................................................................................... 48

Bank/Row Activation ...................................................................................................................................... 49

READ Operation ............................................................................................................................................. 50

WRITE Operation ........................................................................................................................................... 59

Burst Read/Single Write .............................................................................................................................. 66

PRECHARGE Operation .................................................................................................................................. 67

Auto Precharge ........................................................................................................................................... 67

AUTO REFRESH Operation ............................................................................................................................. 79

SELF REFRESH Operation ............................................................................................................................... 81

Power-Down .................................................................................................................................................. 83

Clock Suspend ............................................................................................................................................... 84

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Features

List of Figures

Figure 1: 32 Meg x 4 Functional Block Diagram ................................................................................................. 9

Figure 2: 16 Meg x 8 Functional Block Diagram ............................................................................................... 10

Figure 3: 8 Meg x 16 Functional Block Diagram ............................................................................................... 11

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 12

Figure 5: 60-Ball FBGA (TopView) .................................................................................................................. 13

Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 14

Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 16

Figure 8: 60-Ball TFBGA (x8 Device), 8mm x 16mm – Package Code FB/BB ...................................................... 17

Figure 9: 54-Ball VFBGA (x16 Device), 8mm x 8mm – Package Code F4/B4 ....................................................... 18

Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 21

Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 22

Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 22

Figure 13: ACTIVE Command ........................................................................................................................ 32

Figure 14: READ Command ........................................................................................................................... 33

Figure 15: WRITE Command ......................................................................................................................... 34

Figure 16: PRECHARGE Command ................................................................................................................ 35

Figure 17: Initialize and Load Mode Register .................................................................................................. 43

Figure 18: Mode Register Definition ............................................................................................................... 45

Figure 19: CAS Latency .................................................................................................................................. 48

Figure 20: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 49

Figure 21: Consecutive READ Bursts .............................................................................................................. 51

Figure 22: Random READ Accesses ................................................................................................................ 52

Figure 23: READ-to-WRITE ............................................................................................................................ 53

Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 54

Figure 25: READ-to-PRECHARGE .................................................................................................................. 54

Figure 26: Terminating a READ Burst ............................................................................................................. 55

Figure 27: Alternating Bank Read Accesses ..................................................................................................... 56

Figure 28: READ Continuous Page Burst ......................................................................................................... 57

Figure 29: READ – DQM Operation ................................................................................................................ 58

Figure 30: WRITE Burst ................................................................................................................................. 59

Figure 31: WRITE-to-WRITE .......................................................................................................................... 60

Figure 32: Random WRITE Cycles .................................................................................................................. 61

Figure 33: WRITE-to-READ ............................................................................................................................ 61

Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 62

Figure 35: Terminating a WRITE Burst ............................................................................................................ 63

Figure 36: Alternating Bank Write Accesses ..................................................................................................... 64

Figure 37: WRITE – Continuous Page Burst ..................................................................................................... 65

Figure 38: WRITE – DQM Operation ............................................................................................................... 66

Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 68

Figure 40: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 69

Figure 41: READ With Auto Precharge ............................................................................................................ 70

Figure 42: READ Without Auto Precharge ....................................................................................................... 71

Figure 43: Single READ With Auto Precharge .................................................................................................. 72

Figure 44: Single READ Without Auto Precharge ............................................................................................. 73

Figure 45: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 74

Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 74

Figure 47: WRITE With Auto Precharge ........................................................................................................... 75

Figure 48: WRITE Without Auto Precharge ..................................................................................................... 76

Figure 49: Single WRITE With Auto Precharge ................................................................................................. 77

Figure 50: Single WRITE Without Auto Precharge ............................................................................................ 78

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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