DS28EC20
20Kb 1-Wire EEPROM
GENERAL DESCRIPTION
The DS28EC20 is a 20480-bit,
EEPROM
organized as 80 memory pages of 256 bits each. An
additional page is set aside for control functions.
Data is written to a 32-byte scratchpad, verified, and
then copied to the EEPROM memory. As a special
feature, blocks of eight memory pages can be write
protected or put in EPROM-Emulation mode, where
bits can only be changed from a 1 to a 0 state. The
DS28EC20 communicates over the single-conductor
1-Wire bus. The communication follows the standard
1-Wire protocol. Each device has its own unalterable
and unique 64-bit ROM registration number. The
registration number is used to address the device in
a multidrop 1-Wire net environment.
1-Wire
®
FEATURES
20480 Bits of Nonvolatile (NV) EEPROM
Partitioned into Eighty 256-Bit Pages
Individual 8-Page Groups of Memory Pages
(Blocks) can be Permanently Write Protected or
Put in OTP EPROM-Emulation Mode ("Write to 0")
Read and Write Access Highly Backward-
Compatible to Legacy Devices (e.g., DS2433)
256-Bit Scratchpad with Strict Read/Write
Protocols Ensures Integrity of Data Transfer
200k Write/Erase Cycle Endurance at +25°C
Unique Factory-Programmed 64-Bit Registration
Number Ensures Error-Free Device Selection
and Absolute Part Identity
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
Communicates to Host at 15.4kbps or 90kbps
Using 1-Wire Protocol
Low-Cost TO-92 Package
Operating Range: 4V to 5.25V, -40°C to +85°C
Operating Range: 3.135V to3.465V,
0°C to +70°C (Standard Speed only)
IEC 1000-4-2 Level 4 ESD Protection (±8kV
Contact,
±15kV
Air, Typical) for I/O Pin
APPLICATIONS
Device Authentication
IEEE 1451.4 Sensor TEDS
Ink/Toner Cartridges
Medical Sensors
PCB Identification
Wireless Base Stations
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS28EC20+
-40°C to +85°C 3 TO-92
DS28EC20+T
-40°C to +85°C 3 TO-92, T&R
DS28EC20P+
-40°C to +85°C 6 TSOC
DS28EC20P+T -40°C to +85°C 6 TSOC, T&R
DS28EC20Q+T -40°C to +85°C 6 TDFN, T&R
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
PIN CONFIGURATION
TYPICAL OPERATING CIRCUIT
V
CC
R
PUP
(300Ω
to 2.2kΩ)
PX.Y
I/O
DS28EC20
µC
GND
Commands, bytes, and modes are capitalized for clarity.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
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19-6067; Rev 7; 9/17
DS28EC20: 20Kb 1-Wire EEPROM
ABSOLUTE MAXIMUM RATINGS
I/O Voltage to GND
I/O Sink Current
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow)
TO-92
TSOC, TDFN
-0.5V, +6V
20mA
-40°C to +85°C
+150°C
-55°C to +125°C
+300°C
+250°C
+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
5.0V SUPPLY ELECTRICAL CHARACTERISTICS
(V
PUP
= 4V to 5.25, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
I/O PIN GENERAL DATA
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
(Notes 2, 12)
Rising-Edge Hold-off Time
(Notes 5, 13)
Timeslot Duration
(Notes 2, 14)
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
t
REC
t
REH
t
SLOT
(Notes 2, 3)
(Notes 4, 5)
I/O pin at V
PUP
(Notes 5, 6, 7)
(Notes 2, 8)
(Notes 5, 6, 9)
(Notes 5, 6, 10)
At 4mA (Note 11)
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
2.5
0.30
5
5
0.5
Not applicable (0)
65
11
480
48
15
2
60
8
60
6
60
6
1
1
5
0.800
t
RL
+
δ
t
RL
+
δ
640
80
60
6
240
24
75
10
120
15.5
15
2
15 -
δ
2-
δ
15
2.27
0.3
2000
0.05
1.6
3.5
V
PUP
-
1.8
0.5
V
PUP
-
1.1
1.30
0.20
2.2
kΩ
pF
µA
V
V
V
V
V
µs
5.0
µs
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Reset-Low Time (Note 2)
Presence-Detect High
Time
Presence-Detect Low
Time
Presence-Detect Sample
Time (Notes 2, 15)
I/O PIN, 1-Wire WRITE
Write-0 Low Time
(Notes 2, 16, 17)
Write-1 Low Time
(Notes 2, 17)
I/O PIN, 1-Wire READ
Read-Low Time
(Notes 2, 18)
Read-Sample Time
(Notes 2, 18)
t
RL
t
MSR
µs
µs
t
W0L
t
W1L
µs
µs
t
RSTL
t
PDH
t
PDL
t
MSP
µs
µs
µs
µs
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DS28EC20: 20Kb 1-Wire EEPROM
PARAMETER
EEPROM
Programming Current
Programming Time
Write/Erase Cycles
(Endurance) (Notes 21,
22)
Data Retention
(Notes 23, 24, 25)
Note 1:
Note 2:
Note 3:
SYMBOL
I
PROG
t
PROG
N
CY
t
DR
(Note 19)
(Note 20)
At +25°C
CONDITIONS
MIN
TYP
MAX
0.9
10
UNITS
mA
ms
years
200k
50k
40
At +85°C (worst case)
At +85°C (worst case)
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
Note 25:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is charged, it
does not affect normal communication.
Guaranteed by design, characterization and/or simulation only. Not production tested.
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage which is itself a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on I/O. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of V
TL
, V
TH
,
and V
HY
.
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to V
ILMAX
at all times the master is driving I/O to a logic 0 level.
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least V
HY
to be detected as logic 0.
The I-V characteristic is approximately linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Interval after t
RSTL
during which a bus master can read a logic 0 on I/O if there is a DS28EC20 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
ε
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε,
respectively.
δ
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Current drawn from I/O during the EEPROM programming interval. During a programming cycle the voltage at I/O drops by I
PROG
× R
PUP
below V
PUP
. If V
PUP
and R
PUP
are within their EC table limits, the residual I/O voltage meets the guaranteed-by-design
minimum voltage requirements for programming.
The t
PROG
interval begins t
REHMAX
after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
PROG
to I
L
.
Write-cycle endurance is degraded as T
A
increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
A
increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
PARAMETER
t
SLOT
(incl. t
REC
)
t
RSTL
t
PDH
t
PDL
t
W0L
LEGACY VALUES
STANDARD SPEED
OVERDRIVE SPEED#
MIN
MAX
MIN
MAX
61µs
(undefined)
7µs
(undefined)
480µs
(undefined)
48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs
8µs
24µs
60µs
120µs
6µs
16µs
DS28EC20 VALUES
STANDARD SPEED
OVERDRIVE SPEED#
MIN
MAX
MIN
MAX
65µs*
(undefined)
11µs
(undefined)
480µs
640µs
48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs
8µs
24µs
60µs
120µs
6µs
15.5µs
*Intentional
change, longer recovery time requirement due to modified 1-Wire front-end.
#For
operation at overdrive speed, the DS28EC20 requires V
PUP
to be between 4V and 5.25V.
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DS28EC20: 20Kb 1-Wire EEPROM
3.3V SUPPLY ELECTRICAL CHARACTERISTICS
(V
PUP
= 3.3V ±5%, T
A
= 0°C to +70°C, unless otherwise noted.)
PARAMETER
I/O PIN GENERAL DATA
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
Rising-Edge Hold-off Time
Timeslot Duration
Reset-Low Time
Presence-Detect High
Time
Presence-Detect Low
Time
Presence-Detect Sample
Time
I/O PIN, 1-Wire WRITE
Write-0 Low Time
Write-1 Low Time
I/O PIN, 1-Wire READ
Read-Low Time
Read-Sample Time
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (Endu-
rance) (Notes 19, 20)
Data Retention
I
PROG
t
PROG
N
CY
t
DR
(Note 17)
(Note 18)
At +25°C
At +70°C
(Notes 21, 22, 23)
0.9
10
200k
50k
40
mA
ms
years
t
RL
t
MSR
Standard speed (Notes 1, 16)
Standard speed (Notes 1, 16)
5
t
RL
+
δ
15 -
δ
15
µs
µs
t
W0L
t
W1L
Standard speed (Notes 1, 15)
Standard speed (Notes 1, 15)
60
1
120
15
µs
µs
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
t
REC
t
REH
t
SLOT
t
RSTL
t
PDH
t
PDL
t
MSP
(Notes 1, 2)
(Notes 3, 4)
I/O pin at V
PUP
(Notes 4, 5, 6)
(Notes 1, 7)
(Notes 4, 5, 8)
(Notes 4, 5, 9)
At 4mA (Note 10)
Standard speed (Notes 1, 11)
Standard speed (Notes 4, 12)
Standard speed (Notes 1, 13)
Standard speed (Note 1)
Standard speed
Standard speed
Standard speed (Notes 1, 14)
1.09
0.33
5
0.5
65
480
15
60
60
0.3
2000
0.05
0.49
3.5
V
PUP
-
1.9
0.5
V
PUP
-
1.1
0.70
0.30
5.0
2.2
kΩ
pF
µA
V
V
V
V
V
µs
µs
µs
µs
µs
µs
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
640
60
240
75
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DS28EC20: 20Kb 1-Wire EEPROM
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is charged, it
does not affect normal communication.
Guaranteed by design, characterization and/or simulation only. Not production tested.
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage which is itself a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on I/O. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of V
TL
, V
TH
,
and V
HY
.
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to V
ILMAX
at all times the master is driving I/O to a logic 0 level.
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least V
HY
to be detected as logic 0.
The I-V characteristic is approximately linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Interval after t
RSTL
during which a bus master can read a logic 0 on I/O if there is a DS28EC20 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
ε
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε,
respectively.
δ
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval
should be such that the voltage at I/O is greater than or equal to 3.0V. For 3.3V±5% V
PUP
operation of the DS28EC20, a low-
impedance bypass of R
PUP
, which can be activated during programming, is required.
The t
PROG
interval begins t
REHMAX
after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
PROG
to I
L
.
Write-cycle endurance is degraded as T
A
increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
A
increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
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