MT25TL01GHBB8ESF-0AAT TR datasheet, PDF

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MT25TL01GHBB8ESF-0AAT TR: DescriptionNOR FlashSPI FLASH NOR SLC 128MX8 SOIC DDP; Categorysemiconductor Memory IC NOR flash memory; File Size1MB，88 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT25TL01GHBB8ESF-0AAT TR Overview

NOR FlashSPI FLASH NOR SLC 128MX8 SOIC DDP

MT25TL01GHBB8ESF-0AAT TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	SOP2-16
series	MT25TL
storage	1 Gbit
maximum clock frequency	133 MHz
Interface Type	SPI
organize	128 M x 8
Timing type	Synchronous
Data bus width	8 bit
Supply voltage - min.	2.7 V
Supply voltage - max.	3.6 V
Supply current—max.	35 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 105 C
Encapsulation	Reel
storage type	NOR
speed	133 MHz
standard	Not Supported
Factory packaging quantity	1000

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1Gb, Twin-Quad I/O Serial Flash Memory

Features

Micron Serial NOR Flash Memory

3V, Twin-Quad I/O, 4KB, 32KB, 64KB, Sector Erase

MT25TL01GBBB, MT25TL01GHBB

Features

•

Stacked device (two 512Mb die)

SPI-compatible serial bus interface

Single and double transfer rate (STR/DTR)

Clock frequency

– 133 MHz (MAX) for all protocols in STR

– 90 MHz (MAX) for all protocols in DTR

Dual/quad I/O instruction provides increased

throughput up to 90 MB/s for each die correspond-

ing to 180 MB/s for the twin-quad device

Supported protocols in both STR and DTR

– Extended I/O protocol

– Dual I/O protocol

– Quad I/O protocol

Execute-in-place (XIP)

PROGRAM/ERASE SUSPEND operations

Volatile and nonvolatile configuration settings

Software reset

Additional reset pin for selected part numbers

3-byte and 4-byte addressability mode supported

Dedicated 64-byte OTP area outside main memory

– Readable and user-lockable

– Permanent lock with PROGRAM OTP command

Erase capability

– Die erase

– Sector erase 64KB uniform granularity

– Subsector erase 4KB, 32KB granularity

Security and write protection

– Volatile and nonvolatile locking and software

write protection for each 64KB sector

– Nonvolatile configuration locking

– Password protection

– Hardware write protection: nonvolatile bits

(BP[3:0] and TB) define protected area size

– Program/erase protection during power-up

– CRC detects accidental changes to raw data

Electronic signature

– JEDEC-standard 3-byte signature (BA20h)

– Extended device ID: two additional bytes identify

device factory options

JESD47H-compliant

– Minimum 100,000 ERASE cycles per sector

– Data retention: 20 years (TYP)

Options

• Voltage

– 2.7–3.6V

• Density

– 1Gb

• Device stacking

– B = 2 die and 1 S# pin

– H = 2 die and 2 S# pins

• Device generation

• Die revision

• Pin configuration

– RESET# and HOLD#

• Sector Size

– 64KB

• Packages – JEDEC-standard, RoHS-

compliant

– 16-pin SOP2, 300 mils body width

(SO16W)

– 24-ball T-PBGA, 05/6mm x 8mm

(TBGA24)

• Security Features

– Standard

• Special options

– Standard

– Automotive

• Standard security

• Operating temperature range

– From –40°C to +85°C

– From –40°C to +105°C

Marking

01G

•

09005aef862af504

mt25t-qlkt-L01-xBB-xxT.pdf - Rev. E 10/16 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb, Twin-Quad I/O Serial Flash Memory

Features

Contents

Device Description ........................................................................................................................................... 8

Block Diagram .............................................................................................................................................. 9

Advanced Security Protection ..................................................................................................................... 10

Device Logic Diagram ................................................................................................................................. 11

Signal Assignments ......................................................................................................................................... 12

Signal Descriptions ......................................................................................................................................... 15

Package Dimensions – Package Code: SF ......................................................................................................... 16

Package Dimensions – Package Code: 12 ......................................................................................................... 17

Memory Map – 512Mb Density ....................................................................................................................... 18

Status Register ................................................................................................................................................ 19

Block Protection Settings ............................................................................................................................ 20

Flag Status Register ......................................................................................................................................... 21

Extended Address Register .............................................................................................................................. 22

Internal Configuration Register ....................................................................................................................... 23

Nonvolatile Configuration Register .................................................................................................................. 24

Volatile Configuration Register ........................................................................................................................ 26

Supported Clock Frequencies ..................................................................................................................... 27

Enhanced Volatile Configuration Register ........................................................................................................ 29

Security Registers ........................................................................................................................................... 30

Sector Protection Security Register .................................................................................................................. 31

Nonvolatile and Volatile Sector Lock Bits Security ............................................................................................ 32

Volatile Lock Bit Security Register .................................................................................................................... 32

Device ID Data ............................................................................................................................................... 33

Serial Flash Discovery Parameter Data ............................................................................................................. 34

Command Definitions .................................................................................................................................... 35

Software RESET Operations ............................................................................................................................ 41

RESET ENABLE and RESET MEMORY Commands ....................................................................................... 41

READ ID Operations ....................................................................................................................................... 42

READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 42

READ SERIAL FLASH DISCOVERY PARAMETER Operation .............................................................................. 43

READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 43

READ MEMORY Operations Timings ............................................................................................................... 44

4-BYTE READ MEMORY Operations ................................................................................................................ 50

WRITE ENABLE/DISABLE Operations ............................................................................................................. 51

READ REGISTER Operations ........................................................................................................................... 52

WRITE REGISTER Operations ......................................................................................................................... 53

CLEAR FLAG STATUS REGISTER Operation ..................................................................................................... 55

PROGRAM Operations .................................................................................................................................... 56

4-BYTE PROGRAM Operations ........................................................................................................................ 57

PROGRAM Operations Timings ....................................................................................................................... 58

ERASE Operations .......................................................................................................................................... 61

SUSPEND/RESUME Operations ..................................................................................................................... 63

PROGRAM/ERASE SUSPEND Operations .................................................................................................... 63

PROGRAM/ERASE RESUME Operations ...................................................................................................... 63

ONE-TIME PROGRAMMABLE Operations ....................................................................................................... 65

READ OTP ARRAY Command ...................................................................................................................... 65

PROGRAM OTP ARRAY Command .............................................................................................................. 65

ADDRESS MODE Operations .......................................................................................................................... 67

QUAD PROTOCOL Operations ........................................................................................................................ 67

ENTER or RESET QUAD INPUT/OUTPUT MODE Command ....................................................................... 67

09005aef862af504

mt25t-qlkt-L01-xBB-xxT.pdf - Rev. E 10/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb, Twin-Quad I/O Serial Flash Memory

Features

CYCLIC REDUNDANCY CHECK Operations ....................................................................................................

State Table .....................................................................................................................................................

XIP Mode .......................................................................................................................................................

Activate or Terminate XIP Using Volatile Configuration Register ...................................................................

Activate or Terminate XIP Using Nonvolatile Configuration Register .............................................................

Confirmation Bit Settings Required to Activate or Terminate XIP ..................................................................

Terminating XIP After a Controller and Memory Reset .................................................................................

Power-Up and Power-Down ............................................................................................................................

Power-Up and Power-Down Requirements ..................................................................................................

Power Loss and Interface Rescue .....................................................................................................................

Recovery ....................................................................................................................................................

Power Loss Recovery ...................................................................................................................................

Interface Rescue .........................................................................................................................................

Initial Delivery Status .....................................................................................................................................

Absolute Ratings and Operating Conditions .....................................................................................................

DC Characteristics and Operating Conditions ..................................................................................................

AC Characteristics and Operating Conditions ..................................................................................................

AC Reset Specifications ...................................................................................................................................

Program/Erase Specifications .........................................................................................................................

Revision History .............................................................................................................................................

Rev. E – 10/16 .............................................................................................................................................

Rev. D – 06/16 .............................................................................................................................................

Rev. C – 05/16 .............................................................................................................................................

Rev. B – 02/16 .............................................................................................................................................

Rev. A – 02/15 .............................................................................................................................................

09005aef862af504

mt25t-qlkt-L01-xBB-xxT.pdf - Rev. E 10/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb, Twin-Quad I/O Serial Flash Memory

Features

List of Figures

Figure 1: Part Number Ordering Information .................................................................................................... 2

Figure 2: Block Diagram – Flash Die 1 ............................................................................................................... 9

Figure 3: Block Diagram – Flash Die 2 ............................................................................................................. 10

Figure 4: Logic Diagram – Separate Chip-Select and Clock Signals ................................................................... 11

Figure 5: Logic Diagram – Shared Chip-Select and Clock Signals ..................................................................... 11

Figure 6: 16-Pin, Plastic Small Outline – SO16 (Top View) (Single Chip-Select and Clock) ................................. 12

Figure 7: 16-Pin, Plastic Small Outline – SO16 (Top View) (Dual Chip-Select and Clock) ................................... 12

Figure 8: 24-Ball TBGA – 5 x 5 (Balls Down) (Single Chip-Select and Clock) ...................................................... 13

Figure 9: 24-Ball TBGA – 5 x 5 (Balls Down) (Double Chip-Select and Clock) .................................................... 14

Figure 10: 16-Pin SOP2 – 300 mils Body Width ................................................................................................ 16

Figure 11: 24-Ball T-PBGA (5 x 5 ball grid array) – 6mm x 8mm ........................................................................ 17

Figure 12: Memory Array Segments ................................................................................................................ 22

Figure 13: Internal Configuration Register ...................................................................................................... 23

Figure 14: Sector and Password Protection ..................................................................................................... 30

Figure 15: RESET ENABLE and RESET MEMORY Command ........................................................................... 41

Figure 16: READ ID and MULTIPLE I/O READ ID Commands ......................................................................... 42

Figure 17: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 43

Figure 18: READ – 03h/13h

........................................................................................................................... 44

Figure 19: FAST READ – 0Bh/0Ch

................................................................................................................. 44

Figure 20: DUAL OUTPUT FAST READ – 3Bh/3Ch

......................................................................................... 45

Figure 21: DUAL INPUT/OUTPUT FAST READ – BBh/BCh

............................................................................ 45

Figure 22: QUAD OUTPUT FAST READ – 6Bh/6Ch

........................................................................................ 46

Figure 23: QUAD INPUT/OUTPUT FAST READ – EBh/ECh

............................................................................ 46

Figure 24: QUAD INPUT/OUTPUT WORD READ – E7h

................................................................................. 47

Figure 25: DTR FAST READ – 0Dh/0Eh

.......................................................................................................... 47

Figure 26: DTR DUAL OUTPUT FAST READ – 3Dh

........................................................................................ 48

Figure 27: DTR DUAL INPUT/OUTPUT FAST READ – BDh

............................................................................ 48

Figure 28: DTR QUAD OUTPUT FAST READ – 6Dh

........................................................................................ 49

Figure 29: DTR QUAD INPUT/OUTPUT FAST READ – EDh

............................................................................ 49

Figure 30: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 51

Figure 31: READ REGISTER Timing ................................................................................................................ 52

Figure 32: WRITE REGISTER Timing .............................................................................................................. 54

Figure 33: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 55

Figure 34: PAGE PROGRAM Command .......................................................................................................... 58

Figure 35: DUAL INPUT FAST PROGRAM Command ...................................................................................... 58

Figure 36: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 59

Figure 37: QUAD INPUT FAST PROGRAM Command ..................................................................................... 59

Figure 38: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 60

Figure 39: SUBSECTOR and SECTOR ERASE Timing ....................................................................................... 62

Figure 40: BULK ERASE Timing ...................................................................................................................... 62

Figure 41: PROGRAM/ERASE SUSPEND or RESUME Timing .......................................................................... 64

Figure 42: READ OTP Command .................................................................................................................... 65

Figure 43: PROGRAM OTP Command ............................................................................................................ 66

Figure 44: XIP Mode Directly After Power-On .................................................................................................. 71

Figure 45: Power-Up Timing .......................................................................................................................... 74

Figure 46: AC Timing Input/Output Reference Levels ...................................................................................... 78

Figure 47: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 84

Figure 48: Reset Enable and Reset Memory Timing ......................................................................................... 84

Figure 49: Serial Input Timing ........................................................................................................................ 84

Figure 50: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 85

09005aef862af504

mt25t-qlkt-L01-xBB-xxT.pdf - Rev. E 10/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT25TL01GHBB8ESF-0AAT TR Related Products

	MT25TL01GHBB8ESF-0AAT TR	MT25TL01GHBB8E12-0AAT TR	MT25TL01GBBB8E12-0AAT TR	MT25TL01GBBB8ESF-0AAT TR
Description	NOR FlashSPI FLASH NOR SLC 128MX8 SOIC DDP	NOR FlashSPI FLASH NOR SLC 128MX8 TBGA DDP	NOR FlashSPI FLASH NOR SLC 128MX8 TBGA DDP	NOR FlashSPI FLASH NOR SLC 128MX8 SOIC DDP
Maker	Micron	Micron	Micron	Micron
Product Category	NOR flash memory	NOR flash memory	NOR flash memory	NOR flash memory
Installation style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Package/box	SOP2-16	T-PBGA-24	T-PBGA-24	SOP2-16
series	MT25TL	MT25TL	MT25TL	MT25TL
storage	1 Gbit	1 Gbit	1 Gbit	1 Gbit
maximum clock frequency	133 MHz	133 MHz	133 MHz	133 MHz
Interface Type	SPI	SPI	SPI	SPI
organize	128 M x 8	128 M x 8	128 M x 8	128 M x 8
Timing type	Synchronous	Synchronous	Synchronous	Synchronous
Data bus width	8 bit	8 bit	8 bit	8 bit
Supply voltage - min.	2.7 V	2.7 V	2.7 V	2.7 V
Supply voltage - max.	3.6 V	3.6 V	3.6 V	3.6 V
Supply current—max.	35 mA	35 mA	35 mA	35 mA
Minimum operating temperature	- 40 C	- 40 C	- 40 C	- 40 C
Maximum operating temperature	+ 105 C	+ 105 C	+ 105 C	+ 105 C
Encapsulation	Reel	Reel	Reel	Reel
storage type	NOR	NOR	NOR	NOR
speed	133 MHz	133 MHz	133 MHz	133 MHz
standard	Not Supported	Not Supported	Not Supported	Not Supported
Factory packaging quantity	1000	2500	2500	1000

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