NV25080, NV25160,
NV25320, NV25640
EEPROM Serial
8/16/32/64-Kb SPI
Automotive Grade 0
Description
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NV25080, NV25160, NV25320, NV25640 are a EERPOM Serial
8/16/32/64−Kb SPI Automotive Grade 0 devices internally organized
as 1K/2K/4K/8Kx8 bits. It features a 32−byte page write buffer and
supports the Serial Peripheral Interface (SPI) protocol. The device is
enabled through a Chip Select (CS) input. In addition, the required bus
signals are clock input (SCK), data input (SI) and data output (SO)
lines. The HOLD input may be used to pause any serial
communication with the NV25xxx device. The device features
software and hardware write protection, including partial as well as
full array protection. Byte Level On−Chip ECC (Error Correction
Code) makes the device suitable for high reliability applications. The
device offers an additional Identification Page which can be
permanently write protected.
Features
SOIC−8
DW SUFFIX
CASE 751BD
TSSOP−8
DT SUFFIX
CASE 948AL
PIN CONFIGURATION
CS
SO
WP
V
SS
1
V
CC
HOLD
SCK
SI
•
Automotive Temperatures:
•
•
•
•
•
•
•
•
•
•
SOIC (DW), TSSOP (DT)
V
CC
SI
CS
WP
HOLD
SCK
V
SS
NV25xxx
SO
•
•
•
−
Grade 0:
−40°C
to +150°C / V
CC
= 2.5 V to 5.5 V
10 MHz SPI Compatible
SPI Modes (0,0) & (1,1)
32−byte Page Write Buffer
Self−timed Write Cycle
Hardware and Software Protection
Additional Identification Page with Permanent Write Protection
NV Prefix for Automotive and Other Applications Requiring Site and
Change Control
Block Write Protection
−
Protect
1
/
4
,
1
/
2
or Entire EEPROM Array
Low Power CMOS Technology
Program/Erase Cycles:
−
4,000,000 at 25°C
−
1,200,000 at +85°C
−
600,000 at +125°C
−
300,000 at +150°C
200 Year Data Retention
SOIC, TSSOP 8−lead Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
Figure 1. Functional Symbol
PIN FUNCTION
Pin Name
CS
SO
WP
V
SS
SI
SCK
HOLD
V
CC
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2017
June, 2018
−
Rev. 1
1
Publication Order Number:
NV25080/D
NV25080, NV25160, NV25320, NV25640
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
−45
to +150
−65
to +150
−0.5
to +6.5
Units
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
NEND
Parameter
Endurance
T
A
≤
25°C
T
A
= 85°C
T
A
= 125°C
T
A
= 150°C
TDR
Data Retention
T
A
= 25°C
2. Determined through qualification/characterization.
3. A Write Cycle refers to writing a Byte, a Page, the Status Register or the Identification Page.
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +150°C, unless otherwise specified.)
Symbol
Parameter
Read, SO open
I
CCW
I
SB1
Supply Current
(Write Mode)
Standby Current
Write, CS = V
CC
Write, CS = V
CC
V
IN
= GND or V
CC
,
CS = V
CC
, WP = V
CC
,
HOLD = V
CC
, V
CC
= 5.5 V
V
IN
= GND or V
CC
,
CS = V
CC
, WP = GND,
HOLD = GND, V
CC
= 5.5 V
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +150°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +150°C
−2
−2
−0.5
0.7 V
CC
I
OL
= 3.0 mA
I
OH
=
−1.6
mA
V
CC
−0.8
V
0.6
1.5
Test Conditions
f
SCK
= 10 MHz
Min
Max
3
2
2
3
7
5
10
2
2
0.3 V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
Test Condition
Max
4,000,000
1,200,000
600,000
300,000
200
Year
Units
Write Cycles
(Note 3)
Table 3. DC OPERATING CHARACTERISTICS
I
SB2
Standby Current
I
L
I
LO
V
IL1
V
IH1
V
OL1
V
OH1
V
PORth
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Internal Power−On
Reset Threshold
V
IN
= GND or V
CC
CS = V
CC
, V
OUT
= GND or V
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NV25080, NV25160, NV25320, NV25640
Table 4. PIN CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V) (Note 2)
Symbol
C
OUT
C
IN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Test
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
8
Unit
pF
pF
Table 5. AC CHARACTERISTICS
(Note 4)
V
CC
.
2.5 V
−405C
to +1505C
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 5)
t
FI
(Note 5)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WC
(Note 6)
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
Write Cycle Time
40
30
30
30
30
4
ms
0
20
25
0
10
40
Parameter
Min
DC
10
10
40
40
25
2
2
Max
10
Unit
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
at V
CC
> 2.5 V, 0.2 V
CC
to 0.8 V
CC
at V
CC
< 2.5 V
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 30 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 6. POWER−UP TIMING
(Notes 5, 7)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
0.35
0.35
Unit
ms
ms
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
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NV25080, NV25160, NV25320, NV25640
Pin Description
Functional Description
SI:
The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO:
The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and NV25xxx.
CS:
The chip select input pin is used to enable/disable the
NV25xxx. When CS is high, the SO output is tri−stated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress).
Every communication
session between host and NV25xxx must be preceded by a
high to low transition and concluded with a low to high
transition of the CS input.
WP:
The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD:
The HOLD input pin is used to pause transmission
between host and NV25xxx, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, the HOLD input should be tied to V
CC
, either
directly or through a resistor.
The NV25xxx device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
Reading data stored in the NV25xxx is accomplished by
simply providing the READ command and an address.
Writing to the NV25xxx, in addition to a WRITE command,
address and data, also requires enabling the device for
writing by first setting certain bits in a Status Register, as will
be explained later.
After a high to low transition on the CS input pin, the
NV25xxx will accept any one of the six instruction op−codes
listed in Table 7 and will ignore all other possible 8−bit
combinations. The communication protocol follows the
timing from Figure 2.
The NV25xxx features an additional Identification Page
(32 bytes) which can be accessed for Read and Write
operations when the IPL bit from the Status Register is set
to “1”. The user can also choose to make the Identification
Page permanent write protected.
Table 7. INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Op−code
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
t
CS
CS
t
CNH
SCK
t
SU
SI
t
H
VALID
IN
t
V
t
HO
SO
HI−Z
VALID
OUT
HI−Z
t
V
t
DIS
t
RI
t
FI
t
CSS
t
WH
t
WL
t
CSH
t
CNS
Figure 2. Synchronous Data Timing
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NV25080, NV25160, NV25320, NV25640
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
Table 8. STATUS REGISTER
7
WPEN
6
IPL
5
0
4
LIP
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The IPL (Identification Page Latch) bit determines
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations. The LIP
(Lock Identification Page) bit is set by the user with the
WRSR command and is non−volatile. When set to 1, the
Identification Page is permanently write protected (locked
in Read−only mode).
Note:
The IPL and LIP bits cannot be set to 1 using the same
WRSR instruction. If the user attempts to set (“1”) both the
IPL and LIP bit in the same time, these bits cannot be written
and therefore they will remain unchanged.
3
BP1
2
BP0
1
WEL
0
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
Array Address Protected
None
NV25080: 0300−03FF, NV25160: 0600−07FF,
NV25320: 0C00−0FFF, NV25640: 1800−1FFF
NV25080: 0200−03FF, NV25160: 0400−07FF,
NV25320: 0800−0FFF, NV25640: 1000−1FFF
NV25080: 0000−03FF, NV25160: 0000−07FF,
NV25320: 0000−0FFF, NV25640: 0000−1FFF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 10. WRITE PROTECT CONDITIONS
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
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