MT49H16M18SJ-25:B datasheet, PDF

Datasheet> All Categories > semiconductor> Memory IC> Dynamic random access memory> MT49H16M18SJ-25:B

MT49H16M18SJ-25:B: DescriptionDynamic random access memory RL dynamic random access memory 288M 16MX18 FBGA; Categorysemiconductor Memory IC Dynamic random access memory; File Size6MB，83 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

Download Datasheet Parametric View All

MT49H16M18SJ-25:B Overview

Dynamic random access memory RL dynamic random access memory 288M 16MX18 FBGA

MT49H16M18SJ-25:B Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	RLDRAM2
Data bus width	18 bit
organize	16 M x 18
Package/box	FBGA-144
storage	288 Mbit
maximum clock frequency	533 MHz
Supply voltage - max.	1.9 V
Supply voltage - min.	1.7 V
Supply current—max.	408 mA
Minimum operating temperature	0 C
Maximum operating temperature	+ 95 C
series	MT49H
Encapsulation	Tray
Installation style	SMD/SMT
Factory packaging quantity	1120

Preview

Download Datasheet

View All

288Mb: x9, x18, x36 CIO RLDRAM 2

Features

CIO RLDRAM 2

MT49H32M9 – 32 Meg x 9 x 8 Banks

MT49H16M18 – 16 Meg x 18 x 8 Banks

MT49H8M36 – 8 Meg x 36 x 8 Banks

Features

• 533 MHz DDR operation (1.067 Gb/s/pin data rate)

• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock

frequency)

• Organization

– 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36

• 8 internal banks for concurrent operation and maxi-

mum bandwidth

• Reduced cycle time (15ns at 533 MHz)

• Nonmultiplexed addresses (address multiplexing

option available)

• SRAM-type interface

• Programmable READ latency (RL), row cycle time,

and burst sequence length

• Balanced READ and WRITE latencies in order to

optimize data bus utilization

• Data mask for WRITE commands

• Differential input clocks (CK, CK#)

• Differential input data clocks (DKx, DKx#)

• On-die DLL generates CK edge-aligned data and

output data clock signals

• Data valid signal (QVLD)

• 32ms refresh (8K refresh for each bank; 64K refresh

command must be issued in total each 32ms)

• HSTL I/O (1.5V or 1.8V nominal)

• 25–60Ω matched impedance outputs

• 2.5V V

EXT

, 1.8V V

, 1.5V or 1.8V V

DDQ

I/O

• On-die termination (ODT) R

Options

• Clock cycle timing

– 1.875ns @

RC = 15ns

– 2.5ns @

RC = 15ns

– 2.5ns @

RC = 20ns

– 3.3ns @

RC = 20ns

– 5.0ns @

RC = 20ns

• Configuration

– 32 Meg x 9

– 16 Meg x 18

– 8 Meg x 36

• Operating temperature

– Commercial (0° to +95°C)

– Industrial (T

= –40°C to +95°C;

= –40°C to +85°C)

• Package

– 144-ball µBGA

– 144-ball µBGA (Pb-free)

– 144-ball FBGA

– 144-ball FBGA (Pb-free)

• Revision

Note:

Marking

-18

-25E

-25

-33

-5

32M9

16M18

8M36

None

1. Not all options listed can be combined to

define an offered product. Use the part cat-

alog search on micron.com for available of-

ferings.

PDF: 09005aef80a41b46

rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

288Mb: x9, x18, x36 CIO RLDRAM 2

Features

Contents

General Description ......................................................................................................................................... 7

Functional Block Diagrams ............................................................................................................................... 8

Ball Assignments and Descriptions ................................................................................................................. 11

Package Dimensions ....................................................................................................................................... 16

Electrical Specifications – I

.......................................................................................................................... 18

Absolute Maximum Ratings ............................................................................................................................ 22

AC and DC Operating Conditions .................................................................................................................... 22

Input Slew Rate Derating ................................................................................................................................ 25

Capacitance ............................................................................................................................................... 28

AC Electrical Characteristics ........................................................................................................................... 29

Temperature and Thermal Impedance ............................................................................................................ 32

Commands .................................................................................................................................................... 34

MODE REGISTER SET (MRS) Command ......................................................................................................... 35

Configuration Tables .................................................................................................................................. 37

Burst Length (BL) ....................................................................................................................................... 37

Address Multiplexing .................................................................................................................................. 39

DLL RESET ................................................................................................................................................. 39

Drive Impedance Matching ........................................................................................................................ 39

On-Die Termination (ODT) ......................................................................................................................... 40

READ Command ............................................................................................................................................ 41

WRITE Command .......................................................................................................................................... 42

AUTO REFRESH (AREF) Command ................................................................................................................. 43

INITIALIZATION Operation ............................................................................................................................ 44

READ Operations ........................................................................................................................................... 47

WRITE Operations .......................................................................................................................................... 53

AUTO REFRESH Operation ............................................................................................................................. 58

On-Die Termination ....................................................................................................................................... 59

Multiplexed Address Mode .............................................................................................................................. 62

Configuration Tables .................................................................................................................................. 66

REFRESH Command in Multiplexed Address Mode ..................................................................................... 66

IEEE 1149.1 Serial Boundary Scan (JTAG) ........................................................................................................ 71

Disabling the JTAG Feature ......................................................................................................................... 71

Test Access Port (TAP) ..................................................................................................................................... 71

Test Clock (TCK) ......................................................................................................................................... 71

Test Mode Select (TMS) .............................................................................................................................. 71

Test Data-In (TDI) ...................................................................................................................................... 72

Test Data-Out (TDO) .................................................................................................................................. 72

TAP Controller ................................................................................................................................................ 73

Test-Logic-Reset ......................................................................................................................................... 73

Run-Test/Idle ............................................................................................................................................. 73

Select-DR-Scan .......................................................................................................................................... 73

Capture-DR ................................................................................................................................................ 73

Shift-DR ..................................................................................................................................................... 73

Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 73

Update-DR ................................................................................................................................................. 73

Instruction Register States .......................................................................................................................... 73

TAP Reset ....................................................................................................................................................... 74

TAP Registers ................................................................................................................................................. 75

Instruction Register .................................................................................................................................... 75

Bypass Register .......................................................................................................................................... 75

PDF: 09005aef80a41b46

rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

288Mb: x9, x18, x36 CIO RLDRAM 2

Features

List of Figures

Figure 1: 288Mb RLDRAM 2 CIO Part Numbers ................................................................................................ 2

Figure 2: State Diagram ................................................................................................................................... 7

Figure 3: 32 Meg x 9 Functional Block Diagram ................................................................................................. 8

Figure 4: 16 Meg x 18 Functional Block Diagram ............................................................................................... 9

Figure 5: 8 Meg x 36 Functional Block Diagram ............................................................................................... 10

Figure 6: 144-Ball µBGA ................................................................................................................................. 16

Figure 7: 144-Ball FBGA ................................................................................................................................. 17

Figure 8: Minimum Slew Rate ........................................................................................................................ 23

Figure 9: Clock Input ..................................................................................................................................... 24

Figure 10: Nominal

AS/

CS/

DS and

AH/

CH/

DH Slew Rate .......................................................................... 28

Figure 11: AC Outputs – Equivalent Load ........................................................................................................ 31

Figure 12: Example Temperature Test Point Location ...................................................................................... 33

Figure 13: Mode Register Set .......................................................................................................................... 35

Figure 14: Mode Register Definition in Nonmultiplexed Address Mode ............................................................ 36

Figure 15: Read Burst Lengths ........................................................................................................................ 38

Figure 16: On-Die Termination-Equivalent Circuit .......................................................................................... 40

Figure 17: READ Command ........................................................................................................................... 41

Figure 18: WRITE Command ......................................................................................................................... 42

Figure 19: AUTO REFRESH Command ........................................................................................................... 43

Figure 20: Power-Up/Initialization Sequence ................................................................................................. 45

Figure 21: Power-Up/Initialization Flow Chart ................................................................................................ 46

Figure 22: Basic READ Burst Timing ............................................................................................................... 47

Figure 23: Consecutive READ Bursts (BL = 2) .................................................................................................. 48

Figure 24: Consecutive READ Bursts (BL = 4) .................................................................................................. 49

Figure 25: READ-to-WRITE ............................................................................................................................ 49

Figure 26: Read Data Valid Window for x9 Device ........................................................................................... 50

Figure 27: Read Data Valid Window for x18 Device .......................................................................................... 51

Figure 28: Read Data Valid Window for x36 Device .......................................................................................... 52

Figure 29: WRITE Burst ................................................................................................................................. 53

Figure 30: Consecutive WRITE-to-WRITE ....................................................................................................... 54

Figure 31: WRITE-to-READ ............................................................................................................................ 55

Figure 32: WRITE-to-READ – Separated by Two NOP Commands .................................................................... 56

Figure 33: WRITE – DM Operation ................................................................................................................. 57

Figure 34: AUTO REFRESH Cycle ................................................................................................................... 58

Figure 35: READ Burst with ODT .................................................................................................................... 59

Figure 36: READ-NOP-READ with ODT .......................................................................................................... 60

Figure 37: READ-to-WRITE with ODT ............................................................................................................ 61

Figure 38: Command Description in Multiplexed Address Mode ..................................................................... 62

Figure 39: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 63

Figure 40: Mode Register Definition in Multiplexed Address Mode .................................................................. 64

Figure 41: Burst REFRESH Operation with Multiplexed Addressing ................................................................. 66

Figure 42: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 67

Figure 43: WRITE-to-READ with Multiplexed Addressing ................................................................................ 68

Figure 44: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 69

Figure 45: READ-to-WRITE with Multiplexed Addressing ................................................................................ 70

Figure 46: TAP Controller State Diagram ......................................................................................................... 74

Figure 47: TAP Controller Block Diagram ........................................................................................................ 74

Figure 48: JTAG Operation – Loading Instruction Code and Shifting Out Data .................................................. 78

Figure 49: TAP Timing ................................................................................................................................... 78

PDF: 09005aef80a41b46

rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Recommended Resources

Low-cost high-precision instrument amplification circuit diagram

C-MOS inverter and its internal structure

High performance DC power amplifier drive circuit AP500A-01

Snowflake BCD-191 refrigerator circuit

Circuit diagram of using NCP3065/NCP3066 to drive LED

Capacitor step-down driver LED circuit 2

Design of XPT2046 touch controller based on FPGA: [i=s]This post was last edited by Xinhangxian Paotang on 2017-4-27 11:41[/i] [align=center][color=#000][size=15px][b][size=5]Design of XPT2046 Touch Controller Based on FPGA[/size][/b][/size][/color][...; 芯航线跑堂 FPGA/CPLD

Keeping DC/DC solutions (super) simple for cost-sensitive applications: Transfer from: deyisupport Have you recently upgraded your TV to one with a larger screen and ultra-high-definition resolution? Have you installed a new set-top box with six-channel simultaneous digit...; okhxyyo Analogue and Mixed Signal

Bluetooth serial port module: www.wavesen.com www.linvor.com Original supply of the most cost-effective and lowest price Bluetooth serial port module including AT commands, etc....; oooooooooo Embedded System

Newbie help: After the development board is connected to the PC host, it cannot find the new hardware, why? ?: I just got the yl2440 development board. After connecting it to the PC, the PC crashed when automatically installing new hardware. After restarting, it could no longer find the new hardware. The 10M n...; sun139 Embedded System

Mr. Complaint Quotes: After reading the "past of middle-aged uncles" by netizens and thinking about my own situation, I wrote the following article: Mr. Complaint, male, over 40, is said to have graduated from a famous uni...; 西门 Talking

Difference between LATx and PORTx: The difference between LATx and PORTx, please give me some advice, thank you very much... :)...; dongbin1128 MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components