Data Sheet
FEATURES
K Band Downconverter with Integrated
Fractional-N PLL and VCO
ADMV4420
GENERAL DESCRIPTION
The ADMV4420 is a highly integrated, double balanced, active
mixer with an integrated fractional-N synthesizer, ideally suited
for next generation K band satellite communications.
The RF front end consists of an integrated RF balun and low
noise amplifier (LNA) for an optimal, 7 dB, single-sideband
noise figure while minimizing external components. Additionally,
the high dynamic range IF output amplifier provides a nominal
conversion gain of 36 dB.
An integrated low phase noise, fractional-N, phase-locked loop
(PLL) with a multicore voltage controlled oscillator (VCO) and
internal 2× multiplier generate the necessary on-chip LO signal
for the double balanced mixer, eliminating the need for external
frequency synthesis. The multicore VCO uses an internal
autocalibration routine that allows the PLL to select the
necessary settings and lock in approximately 400 µs.
The reference input to the PLL employs a differentially excited
50 MHz crystal oscillator. Alternatively, the reference input can
be driven by an external, singled-ended, 50 MHz source. The
phase frequency detector (PFD) comparison frequency of the
PLL operates up to 50 MHz.
The ADMV4420 is fabricated on a silicon germanium (SiGe),
bipolar complementary metal-oxide semiconductor (BiCMOS)
process, and is available in a 32-lead, RoHS compliant, 5 mm ×
5 mm LFCSP package with an exposed pad. The device is
specified over the −40°C to +85°C temperature range on a 5 V
power supply.
RF front end with integrated RF balun and LNA
Double balanced, active mixer with high dynamic range IF
amplifier
Fractional-N synthesizer with low phase noise, multicore VCO
5 V supply operation with integrated LDO regulators
Output P1dB: 7 dBm
Output IP3: 16 dBm
Conversion gain: 36 dB
Noise figure: 7 dB
RF input frequency range: 16.95 GHz to 22.05 GHz
Internal LO frequency range: 16.75 GHz to 21.15 GHz
IF frequency range: 900 MHz to 2500 MHz
Single-ended 50 Ω input impedance and 75 Ω IF output
impedance
Programmable via 4-wire SPI
32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Satellite communication
Point to point microwave communication
Rev. 0
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ADMV4420
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Interface Schematics..................................................................... 8
Typical Performance Characteristics ............................................. 9
IF = 900 MHz, Low-Side Injection LO Performance .............. 9
IF = 900 MHz, High-Side Injection LO Performance ........... 11
IF = 1700 MHz, Low-Side Injection LO Performance .......... 13
IF = 1700 MHz, High-Side Injection LO Performance ......... 15
IF = 2500 MHz, Low-Side Injection LO Performance .......... 17
IF = 2500 MHz, High-Side Injection LO Performance ......... 19
LO = 16.75 GHz, Low-Side Injection Performance ............... 21
LO = 16.75 GHz, High-Side Injection Performance ............. 23
LO = 18.95 GHz, Low-Side Injection Performance ............... 25
LO = 18.95 GHz, High-Side Injection Performance ............. 27
LO = 21.15 GHz, Low-Side Injection Performance ............... 29
LO = 21.15 GHz, High-Side Injection Performance ............. 31
Phase Noise Performance .......................................................... 33
Return Loss and Isolation.......................................................... 34
Spurious and Harmonics Performance ................................... 35
Theory of Operation ...................................................................... 36
Reference Input Stage................................................................. 36
Reference Doubler, R Counter, and RDIV2 ............................ 36
N Counter .................................................................................... 37
INT, FRAC, MOD, and Reference Path Relationship ............ 37
Integer-N Mode .......................................................................... 37
Phase Frequency Detector and Charge Pump ........................ 37
Loop Filter ................................................................................... 38
CP Current Setup ....................................................................... 38
Bleed Current (CP_BLEED) setup ........................................... 38
MUXOUT.................................................................................... 38
Digital Lock Detect .................................................................... 39
Enables ......................................................................................... 39
Data Sheet
IF Output—External Inductor/Biasing ................................... 39
SPI Configuration ...................................................................... 39
VCO Autocalibration and Automatic Level Control............. 39
Programming Sequence ............................................................ 39
Control Registers ............................................................................ 40
Register Details ............................................................................... 41
Address 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG_1 .. 41
Address 0x001, Reset: 0x00, Name: ADI_SPI_CONFIG_2 .. 42
Address 0x003, Reset: 0x01, Name: CHIPTYPE.................... 43
Address 0x004, Reset: 0x03, Name: PRODUCT_ID_L ........ 43
Address 0x005, Reset: 0x00, Name: PRODUCT_ID_H ....... 43
Address 0x00A, Reset: 0x00, Name: SCRATCHPAD............ 43
Address 0x00B, Reset: 0x00, Name: SPI_REV........................ 43
Address 0x103, Reset: 0x6F, Name: ENABLES....................... 44
Address 0x108, Reset: 0x05, Name: SDO_LEVEL ................. 44
Address 0x200, Reset: 0xA7, Name: INT_L ........................... 45
Address 0x201, Reset: 0x00, Name: INT_H ........................... 45
Address 0x202, Reset: 0x02, Name: FRAC_L ......................... 45
Address 0x203, Reset: 0x00, Name: FRAC_M ....................... 45
Address 0x204, Reset: 0x00, Name: FRAC_H ........................ 45
Address 0x208, Reset: 0x04, Name: MOD_L ......................... 46
Address 0x209, Reset: 0x00, Name: MOD_M ........................ 46
Address 0x20A, Reset: 0x00, Name: MOD_H........................ 46
Address 0x20C, Reset: 0x01, Name: R_DIV_L ...................... 47
Address 0x20D, Reset: 0x00, Name: R_DIV_H ..................... 47
Address 0x20E, Reset: 0x00, Name: REFERENCE ................ 47
Address 0x211, Reset: 0x00, Name:
VCO_DATA_READBACK1 ..................................................... 48
Address 0x212, Reset: 0x00, Name:
VCO_DATA_READBACK2 ..................................................... 48
Address 0x213, Reset: 0x01, Name: PLL_MUX_SEL ............ 49
Address 0x214, Reset: 0x98, Name: LOCK_DETECT .......... 49
Address 0x215, Reset: 0x00, Name: VCO_BAND_SELECT 50
Address 0x216, Reset: 0x00, Name: VCO_ALC_TIMEOUT50
Address 0x217, Reset: 0x01, Name: VCO_MANUAL........... 50
Address 0x219, Reset: 0x13, Name: ALC ................................ 50
Address 0x21C, Reset: 0x90, Name: VCO_TIMEOUT1 ...... 51
Address 0x21D, Reset: 0x01, Name: VCO_TIMEOUT2 ...... 51
Address 0x21E, Reset: 0x4B, Name: VCO_BAND_DIV ...... 51
Address 0x21F, Reset: 0x18, Name:
VCO_READBACK_SEL ........................................................... 51
Rev. 0 | Page 2 of 60
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