QL4058-4PB456I datasheet, PDF - EEWORLD Datasheet

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QL4058-4PB456I: Description58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM; File Size260KB，23 Pages; ManufacturerETC

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QL4058-4PB456I Overview

58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM

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QL4058 QuickRAM Data Sheet

• • • • • •

58,000 Usable PLD Gate QuickRAM ESP Combining Performance,

Density and Embedded RAM

Device Highlights

High Performance & High Density

•

58,000 Usable PLD Gates with 252 I/Os

•

300 MHz 16-bit Counters, 400 MHz

Advanced I/O Capabilities

•

Interfaces with both 3.3 V and 5.0 V devices

•

PCI compliant with 3.3 V and 5.0 V busses

Datapaths, 160+ MHz FIFOs

•

0.35

µm

four-layer metal non-volatile

CMOS process for smallest die sizes

for -1/-2/-3/-4 speed grades

•

Full JTAG boundary scan

•

I/O Cells with individually controlled

Registered Input Path and Output Enables

High Speed Embedded SRAM

•

18 dual-port RAM modules, organized in

user-configurable 1,152 bit blocks

•

5 ns access times, each port independently

accessible

•

Fast and efficient for FIFO, RAM, and ROM

functions

RAM

Blocks

1,008

High Speed

Logic Cells

Easy to Use / Fast Development

Cycles

•

100% routable with 100% utilization and

Interface

complete pin-out stability

•

Variable-grain logic cells provide high

performance and 100% utilization

•

Comprehensive design tools include high

quality Verilog/VHDL synthesis

Figure 1: QuickRAM Block Diagram

www.quicklogic.com

•

QL4058 QuickRAM Data Sheet Rev H

Architecture Overview

The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in

combination with Dual-Port SRAM modules. The QL4058 is a 58,000 usable PLD gate

member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35

µm

four-layer metal process using QuickLogic's patented ViaLink

TM

technology to provide a

unique combination of high performance, high density, low cost, and extreme ease-of-use.

The QL4058 contains 1,008 logic cells and 18 Dual Port RAM modules (see

Figure 1

). Each

RAM module has 1,152 RAM bits, for a total of 20,736 bits. RAM Modules are Dual Port

(one read port, one write port) and can be configured into one of four modes:

64 (deep)

18 (wide), 128

9, 256

4, or 512

2 (see

Figure 4

). With a maximum of

252 I/Os, the QL4058 is available in 208-PQFP, 240-pin PQFP, and 456-pin PBGA

packages.

Designers can cascade multiple RAM modules to increase the depth or width allowed in

single modules by connecting corresponding address lines together and dividing the words

between modules (see

Figure 2

). This approach allows up to 512-deep configurations as

large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.

Software support for the complete QuickRAM family, including the QL4058, is available

through two basic packages. The turnkey QuickWorks

TM

package provides the most

complete ESP software solution from design entry to logic synthesis, to place and route, to

simulation. The QuickTools package provides a solution for designers who use Cadence,

Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for

design entry, synthesis, or simulation.

The QuickLogic

TM

variable grain logic cell features up to 16 simultaneous inputs and five

outputs within a cell that can be fragmented into five independent cells. Each cell has a fan-

in of 29 including register and control lines (see

Figure 3

WDATA

RAM

Module

(1,152 bits)

RDATA

WADDR

RADDR

RAM

Module

(1,152 bits)

WDATA

RDATA

Figure 2: QuickRAM Module Bits

•

www.quicklogic.com

•

QL4058 QuickRAM Data Sheet Rev H

Product Summary

Total of 252 I/O Pins

•

244 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

•

8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

•

Two array clock/control networks available to the logic cell flip-flop clock, set and reset

inputs—each driven by an input-only pin

•

Six global clock/control networks available to the logic cell F1, clock, set and reset inputs

and the input and I/O register clock, reset and enable inputs as well as the output enable

control—each driven by an input-only or I/O pin, or any logic cell output or I/O cell

feedback

High Performance Silicon

•

Input + logic cell + output total delays = under 6 ns

•

Data path speeds over 400 MHz

•

Counter speeds over 300 MHz

•

FIFO speeds over 160+ MHz

www.quicklogic.com

•

QL4058 QuickRAM Data Sheet Rev H

•

www.quicklogic.com

•

QL4058 QuickRAM Data Sheet Rev H

Electrical Specifications

AC Characteristics at V

= 3.3 V, TA = 25°C (K = 1.00)

To calculate delays, multiply the appropriate K factor from

Table 10: Operating Range

by the

following numbers in the tables provided.

Figure 3: QuickRAM Logic Cell

Table 1: Logic Cell

Symbol

Parameter

CLK

CWHI

CWLO

SET

RESET

Combinatorial Delay

Setup Time

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

Reset Width

1.4

1.7

0.0

0.7

1.2

1.0

0.8

1.9

1.8

Propagation Delays (ns)

Fanout (5)

1.7

0.0

1.0

1.2

1.3

1.1

1.9

1.8

1.9

1.7

0.0

1.2

1.5

1.3

1.9

1.8

2.2

1.7

0.0

1.5

1.2

1.8

1.6

1.9

1.8

3.2

1.7

0.0

2.5

1.2

2.8

2.6

1.9

1.8

a. These limits are derived from a representative selection of the slowest paths through the

QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should

be determined from timing analysis of your particular design.

www.quicklogic.com

•

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