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IDTCSP5993-5Q

Description
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28
Categorylogic   
File Size116KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

IDTCSP5993-5Q Overview

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28

IDTCSP5993-5Q Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionQSOP-28
Contacts28
Reach Compliance Codecompliant
Is SamacsysN
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G28
JESD-609 codee0
length9.9 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals28
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.7 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9116 mm
minfmax85 MHz
Base Number Matches1
IDTCSP5993
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
FEATURES:
3 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 6.25MHz to 100MHz
2x, 4x, 1/2, and 1/4 outputs
5V with TTL outputs
3 skew grades:
CSP5993-2: t
SKEW0
<250ps
CSP5993-5: t
SKEW0
<500ps
CSP5993-7: t
SKEW0
<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA I
OL
high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50Ω terminated lines
Available in QSOP Package
IDTCSP5993
DESCRIPTION:
The CSP5993 is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The CSP5993 has six programmable skew
outputs and two zero skew outputs. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
FUNCTIONAL BLOCK DIAGRAM
G ND/sOE
Skew
Select
3
3
1F1:0
V
CCQ
/PE
Skew
Select
REF
PLL
FB
3
FS
Skew
Select
3
3
3F1:0
3
3
2F1:0
1Q
0
1Q
1
2Q
0
2Q
1
3Q
0
3Q
1
4Q
0
4Q
1
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
1
c
2000
Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-5811/-

IDTCSP5993-5Q Related Products

IDTCSP5993-5Q IDTCSP5993-5QI IDTCSP5993-7QI IDTCSP5993-7Q IDTCSP5993-2Q
Description PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28 PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28 PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28 PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28 PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28
Is it lead-free? Contains lead Contains lead Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SOIC SOIC SOIC SOIC SOIC
package instruction QSOP-28 QSOP-28 QSOP-28 SSOP, SSOP,
Contacts 28 28 28 28 28
Reach Compliance Code compliant compliant compliant compliant compli
Input adjustment STANDARD STANDARD STANDARD STANDARD STANDARD
JESD-30 code R-PDSO-G28 R-PDSO-G28 R-PDSO-G28 R-PDSO-G28 R-PDSO-G28
JESD-609 code e0 e0 e0 e0 e0
length 9.9 mm 9.9 mm 9.9 mm 9.9 mm 9.9 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Number of functions 1 1 1 1 1
Number of terminals 28 28 28 28 28
Actual output times 8 8 8 8 8
Maximum operating temperature 70 °C 85 °C 85 °C 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP SSOP SSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.7 ns 0.7 ns 1 ns 1 ns 0.5 ns
Maximum seat height 1.75 mm 1.75 mm 1.75 mm 1.75 mm 1.75 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.25 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.75 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES
Temperature level COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL
Terminal surface TIN LEAD TIN LEAD TIN LEAD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm 0.635 mm 0.635 mm 0.635 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 3.9116 mm 3.9116 mm 3.9116 mm 3.9116 mm 3.9116 mm
minfmax 85 MHz 85 MHz 85 MHz 85 MHz 85 MHz
Is Samacsys N N N - -
Base Number Matches 1 1 1 - -
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