Memory Time Switch CMOS
(MTSC)
PEB 2045
PEF 2045
Preliminary Data
CMOS IC
1
Features
systems
Switching of up to 512 incoming PCM channels to up to
256 outgoing PCM channels
16-input and 8-output PCM lines
Different kinds of modes (2048, 4096, 8192 kbit/s or mixed
mode)
Configurable for primary access and standard applications
Programmable clock shift with half clock step resolution for
input and output in primary access configuration
Configurable for a 4096- and 8192-kHz device clock
Tristate function for further expansion and tandem
operation
Tristate control signals for external drivers in primary
access configuration
2048-kHz clock output in primary access configuration
Space switch mode
8-bit
µP
interface
Single + 5 V power supply
Advanced low power CMOS technology
Pin and software compatible to the PEB 2040
q
Time/space switch for 2048-, 4096- or 8192-kbit/s PCM
q
q
q
q
q
q
q
q
q
q
q
q
q
q
P-LCC-44
P-DIP-40
Type
PEB 2045-N
PEB 2045-P
PEF 2045-N
PEF 2045-P
Version
VA3
VA3
VA3
VA3
Ordering Code
Q67100-H8602
Q67100-H8322
Q67100-H6055
Q67100-H6056
Package
P-LCC-44 (SMD)
P-DIP-40
P-LCC-44 (SMD)
P-DIP-40
Semiconductor Group
1
01.94
PEB 2045
PEF 2045
Pin Configurations
(top view)
P-LCC-44
P-DIP-40
Semiconductor Group
2
PEB 2045
PEF 2045
1.1
Pin Definitions and Functions
Pin No.
P-DIP
1
2
Symbol
Input (I)
Function
Output (O)
I
I
Ground
(OV)
Synchronization Pulse:
The PEx 2045 is
synchronized relative to the PCM system via
this line.
PCM-Input Ports:
Serial data is received at
these lines at standard TTL levels.
Pin No.
P-LCC
1
3
V
SS
SP
4
7
9
11
13
14
15
16
17
18
19
5
8
10
12
20
3
5
7
9
11
12
13
14
15
16
17
4
6
8
10
18
IN1
IN5
IN9
IN13
IN14
IN15
IN10
IN11
IN6
IN7
IN2
IN0/TSC0
IN4/TSC1
IN8/TSC2
IN12/TSC3
IN3/DCL
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
PCM-Input Port / Tristate Control:
In standard
configuration these pins are used as input lines,
in primary access configuration they supply
control signals for external devices.
PCM-Input Port / Data Clock:
In standard
configuration IN3 is the PCM input line 3, in
primary access configuration it provides a
2048-kHz data clock for the synchronous
interface.
Address 0:
When high, the indirect register
access mechanism is enabled. If A0 is logical 0
the mode and status registers can be written to
and read respectively.
Chip Select:
A low level selects the PEx 2045
for a register access operation.
Supply voltage:
5 V
±
5 %.
Read:
This signal indicates a read operation
and is internally sampled only if CS is active.
The MTSC puts data from the selected internal
register on the data bus with the falling edge of
RD. RD is active low.
21
19
A0
I
22
23
24
20
21
22
CS
I
I
I
V
DD
RD
Semiconductor Group
3
PEB 2045
PEF 2045
Pin Definitions and Functions
(cont’d)
Pin No.
P-LCC
25
Pin No.
P-DIP
23
Symbol
WR
Input (I)
Function
Output (O)
I
Write:
This signal initiates a write operation.
The WR input is internally sampled only if CS is
active. In this case the MTSC loads an internal
register with data from the data bus at the rising
edge of WR. WR is active low.
Data Bus:
The data bus is used for
communication between the MTSC and a
processor.
26
27
29
30
31
32
33
34
35
36
37
38
40
41
42
43
44
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
CLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
0
0
0
0
0
0
0
I
PCM-Output Port:
Serial data is sent by these
lines at standard CMOS or TTL levels. These
pins can be tristated.
Clock:
4096- or 8192-kHz device clock.
Semiconductor Group
4
PEB 2045
PEF 2045
1.2
Functional Symbol
Figure 1
Functional Symbol for the Standard Configuration
Figure 2
Functional Symbol for the Primary Access Configuration
Semiconductor Group
5
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