SPANSION Flash Memory
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20867-5E
FLASH MEMORY
CMOS
2M (256K
×
8/128K
×
16) BIT
MBM29F200TC
-55/-70/-90
/MBM29F200BC
-55/-70/-90
s
GENERAL DESCRIPTION
The MBM29F200TC/BC is a 2M-bit, 5.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K
words of 16 bits each. The MBM29F200TC/BC is offered in a 48-pin TSOP (1) and 44-pin SOP packages. This
device is designed to be programmed in-system with the standard system 5.0 V V
CC
supply. 12.0 V V
PP
is not
required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29F200TC/BC offers access times 55 ns and 90 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
(Continued)
s
PRODUCT LINE-UP
Part No.
Ordering Part No.
V
CC
= 5.0 V ± 5%
V
CC
= 5.0 V ± 10%
-55
—
55
55
30
MBM29F200TC/MBM29F200BC
—
-70
70
70
30
—
-90
90
90
35
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
s
PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
44-pin plastic SOP
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(FPT-44P-M16)
MBM29F200TC
-55/70/90
/MBM29F200BC
-55/70/90
(Continued)
The MBM29F200TC/BC is pin and command set compatible with JEDEC standard. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar
to reading from12.0 V Flash or EPROM devices.
The MBM29F200TC/BC is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).
The devices also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F200TC/BC is erased when shipped from the factory.
The devices features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F200TC/BC memory electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29F200TC
-55/70/90
/MBM29F200BC
-55/70/90
s
FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 write/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low Vcc write inhibit
≤
3.2 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Hardware RESET pin
Resets internal state machine to the read mode
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection
Hardware method temporarily enables any combination of sectors from write on erase operations.
* : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MBM29F200TC
-55/70/90
/MBM29F200BC
-55/70/90
s
PIN ASSIGNMENTS
TSOP (1)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
N.C.
N.C.
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SOP
(Top View)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
N.C.
RY/BY
N.C.
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
V
SS
(FPT-48P-M19)
OE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N.C.
N.C.
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
14
15
16
17
18
19
20
21
22
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
44
43
42
41
40
39
38
37
36
35
34
33
32
RESET
WE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
(Marking Side)
MBM29F200TC/MBM29F200BC
Normal Bend
(Marking Side)
MBM29F200TC/MBM29F200BC
Reverse Bend
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
(FPT-44P-M16)
(FPT-48P-M20)
Pin name
A
16
to A
0
, A
-1
DQ
15
to DQ
0
CE
OE
WE
RY/BY
RESET
BYTE
N.C.
V
SS
4
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Ready-Busy Output
Function
Hardware Reset Pin/Temporary Sector Unprotection
Selects 8-bit or 16-bit mode
No Internal Connection
Device Ground
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