M4A5-32/32-6VC48 datasheet, PDF

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M4A5-32/32-6VC48: DescriptionEE PLD, 6ns, 32-Cell, CMOS, PQFP48, TQFP-48; CategoryProgrammable logic Programmable logic devices; File Size3MB，62 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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M4A5-32/32-6VC48 Overview

EE PLD, 6ns, 32-Cell, CMOS, PQFP48, TQFP-48

M4A5-32/32-6VC48 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QFP
package instruction	TQFP-48
Contacts	48
Reach Compliance Code	not_compliant
ECCN code	EAR99
Is Samacsys	N
Other features	YES
maximum clock frequency	95.2 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G48
JESD-609 code	e0
JTAG BST	YES
length	7 mm
Dedicated input times
Number of I/O lines	32
Number of macro cells	32
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP48,.35SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Programmable logic type	EE PLD
propagation delay	6 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
Base Number Matches	1

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MACH 4 CPLD Family

High Performance EE CMOS

Programmable Logic

FEATURES

High-performance, EE CMOS 3.3-V & 5-V CPLD families

Flexible architecture for rapid logic designs

MAC nclude

Adv

anc 4A Fam

e In

form ily

atio

— Excellent First-Time-Fit

and reﬁt feature

— SpeedLocking

performance for guaranteed ﬁxed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

High speed

— 5.0ns t

Commercial and 7.5ns t

Industrial

— 182MHz f

CNT

32 to 512 macrocells; 32 to 768 registers

44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— JTAG (IEEE 1149.1) compliant for boundary scan testing

— 3.3-V & 5-V JTAG in-system programming

— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system designs

— Programmable pull-up or Bus-Friendly

inputs and I/Os

— Hot-socketing

— Programmable security bit

— Individual output slew rate control

Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— Programmable polarity

— Reset/ preset swapping

Advanced EE CMOS process provides high-performance, cost-effective solutions

Supported by Vantis DesignDirect

software for rapid logic development

— Supports HDL design methodologies with results optimized for Vantis

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice/Vantis and third-party hardware programming support

— Lattice/VantisPRO

(formerly known as MACHPRO

) software for in-system programmability

support on PCs and automated test equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

Publication#

17466

Amendment/0

Rev:

Issue Date:

May 1999

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